Surface-particle interactions in the chemical mechanical polishing process

1997 ◽  
Vol 501 ◽  
Author(s):  
J. J. Adler ◽  
Y. I. Rabinovich ◽  
R. K. Singh ◽  
B. M. Moudgil

ABSTRACTChemical mechanical polishing (CMP) is a critical step in the fabrication of integrated circuits. Each layer of deposited material must be planarized before the next layer of circuitry can be formed. In CMP, a chemically active solution is used to modify the substrate so that a particulate abrasive may polish more efficiently. Modification of the surface often requires high oxidizer concentrations or pH extremes. Under these circumstances the stability of the polishing slurry and prevention of particulate attachment to the substrate is a difficult problem. In this study, atomic force microscopy (AFM) has been used to directly measure the forces between surfaces that simulate those in CMP. Initial investigation has focused on modeling the polishing of tungsten interconnect material by alumina slurries at acidic pH and evaluating the role surfactants can play in the stabilization of the polishing slurry and CMP processes.

2016 ◽  
Vol 1136 ◽  
pp. 305-310 ◽  
Author(s):  
Hyun Seop Lee

Lithium tantalate (LiTaO3) has piezoelectric, electro-optical and nonlinear optical characteristics, and a wide transparency range going from ultraviolet to infrared. It is desirable that LiTaO3 wafer was a smooth surface in order to function with good quality. Chemical mechanical polishing (CMP) has been used to planarize integrated circuits (ICs) or obtain a high surface quality of the substrates. This paper investigates the effect of citric acid as an additive in the slurry for LiTaO3 CMP. The roughness of the wafers was measured by an atomic force microscopy (AFM, XE-100) after polishing. The slurry, which contains citric acid as an additive, has a higher material removal rate and friction force than a slurry without an additive. After polishing, the surface roughness of the LiTaO3 wafer can be reduced down to 1.7Å of Ra.


2005 ◽  
Vol 20 (5) ◽  
pp. 1139-1145 ◽  
Author(s):  
Jeremiah T. Abiade ◽  
Wonseop Choi ◽  
Rajiv K. Singh

To understand the ceria–silica chemical mechanical polishing (CMP) mechanisms, we studied the effect of ceria slurry pH on silica removal and surface morphology. Also, in situ friction force measurements were conducted. After polishing; atomic force microscopy, x-ray photoelectron spectroscopy, and scanning electron microscopy were used to quantify the extent of the particle–substrate interaction during CMP. Our results indicate the silica removal by ceria slurries is strongly pH dependent, with the maximum occurring near the isoelectric point of the ceria slurry.


Author(s):  
Joseph Bonivel ◽  
Sarah Biltz ◽  
Elon Terrell ◽  
Burak Ozdoganlar ◽  
C. Fred Higgs

Chemical mechanical polishing (CMP) is a critical nanomanufacturing process used to remove or planarize ultrathin metallic, dielectric, or barrier layers on silicon wafers. The CMP process is a vital interim fabrication step for integrated circuits and data storage devices. One of the major shortcomings of existing CMP models is that they do not account for crystallographic effects of the thin film metal materials when predicting material removal rates. This work investigates the effect of the microstructure on the CMP of copper and metal thin films on silicon wafer. Nanoindentation tests were conducted to measure the hardness variations across a wafer surface due to the crystallography of the metal films. Spatial variation of mechanical properties was also input into an existing multi-scale CMP model. Nano-characterization and CMP experimental results are presented and compared to an existing CMP wear model.


Author(s):  
Joo Hoon Choi ◽  
Yangro Lee ◽  
Louis E. DeMarco ◽  
Richard T. Leveille ◽  
Joseph A. Levert ◽  
...  

The feature sizes on Integrated Circuits (ICs) continue to decrease to provide higher device densities and smaller chip designs. To accomplish this, current fabrication and processing technology must be advanced to achieve these goals. In particular, Chemical Mechanical Polishing (CMP), which is used for planarization of wafers and logic circuit components during IC fabrication, can cause severe surface damage to components in the form of delamination or distortion of surface features. CMP utilizes polishing particles suspended between a polymeric pad and the substrate to be polished. To control the process with higher precision the fundamentals of friction between CMP surfaces need to be analyzed. To investigate the friction contributions of the polishing particles in the CMP process, individual CMP abrasive particles are modeled by a silica atomic force microscope (AFM) probe with a radius of curvature on the order of 200 nm that is utilized in a scanning probe microscope (SPM). Lateral forces are measured that occur in simulated polishing of silica substrates and polyurethane pad material in a liquid environment. Results are obtained as a function of pH and environment and are compared with macroscopic friction results obtained using a high precision tribometer with a glass ball.


1997 ◽  
Vol 477 ◽  
Author(s):  
Anda McAfee ◽  
Daniel A. Koos ◽  
Stephen mcArdle ◽  
Mercedes Jacobs ◽  
Robert Hiatt

ABSTRACTThis paper addresses an important process issue in tie integration of chemical mechanical polishing (CMP) with interlayer dielectric (ILD) deposition for advanced back end processing. Gap fill between metal lines is achieved by using a dep-etch-dep technique for the tetraethylorthosilicate (TEOS) ILD deposition. The ILD layer is then planarized by CMP. Vias are etched through the ILD and filled with tungsten plugs in a blanket tungsten deposition and tungsten CMP sequence. Delamination has been observed at the interface between the TEOS layers following the blanket tungsten deposition and before or during tungsten CMP. The weak interface between the TEOS layers was found to be the result of residual carbon and fluorine from the tetraflouromethane (CF4) doped etch process. The interface between the TEOS layers was examined using X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). Experiments were carried out to determine if the residue and subsequent delamination could be eliminated by modifying the dep-etch-dep process. An improved process was identified and has been implemented on a 0.5μm CMOS and mixed-mode BiCMOS production line with no subsequent occurrence of interfacial delamination.


1997 ◽  
Vol 476 ◽  
Author(s):  
G.-R. Yang ◽  
Y.-P. Zhao ◽  
Jan M. Neirynck ◽  
Shyam P. Murarka ◽  
Ronald J. Gutmann

AbstractThe quality of benzocyclobutene (BCB) and Parylene-N (PA-N) films after chemical-mechanical polishing (CMP) is influenced by 3 factors: slurry composition, quality of the as-deposited film or post-deposition treated film, and polishing time. The quality of the films has been investigated by using X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). It is shown that the higher the quality of the as-deposited film (or post-deposition treated film), the higher the quality of the polished film. The polishing time has little effect on the surface characteristics of high quality PA-N films, however it has an effect on BCB film. This is attributed to the structure and thermal-stability and higher chemical resistance of PA-N. The RMS surface roughness measured by AFM, for as-deposited PA-N is 90Å. The roughness after CMP processes is greater than 200Å. The roughness for as-spin-coated and polished BCB film is 5A, and 20Å, respectively. The morphology of the PA-N film, either as-deposited or polished, is not as good as the BCB film. A slurry which is good for BCB polishing is not good for PA-N polishing, and vice versa. These results indicate that the nature of the polymer film, including its chemical structure as well as the quality of the as-deposited/post-deposition treated film, plays an important role in polymer CMP.


Author(s):  
Jon C. Lee ◽  
J. H. Chuang

Abstract As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.


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