Gate Stack Formation using a Fully Integrated Single Wafer Cluster Tool

1997 ◽  
Vol 470 ◽  
Author(s):  
David C. Frystak ◽  
John Kuehne ◽  
Rick Wise ◽  
Burt Fowler ◽  
Phil Grothe ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Chemical Vapor ◽  
Breakdown Field ◽  
Fully Integrated ◽  
Low Field ◽  
Yield Values ◽  
Dielectric Charge ◽  
Cluster Tool

ABSTRACTA single wafer gate cluster tool has been evaluated in an effort to quantify the effects of gate clustering on defect density, process capability and device performance. The single wafer gate cluster tool consists of a hydrofluoric vapor (HF-vapor) pre-gate cleanup module, a rapid thermal oxidation (RTO) module and a polysilicon rapid thermal chemical vapor deposition (RTCVD) module. The gate dielectric charge to breakdown (Qbd) of capacitor structures formed using the integrated single wafer gate cluster tool process sequence typically averaged 9.1 to 12.3 coulombs per square centimeter (C/cm2). Excellent gate oxide integrity yield values in the range of 99.8% to 100% were also routinely obtained. The films were free of low field and mid field gate dielectric breakdown events and the devices exhibited dielectric breakdown field strength in excess of fourteen megavolts per centimeter (MV/cm). The cluster tool process was successfully integrated into a transistor device flow. The characteristics of devices formed using the cluster tool process were equivalent to those of devices formed using conventional batch processing at the gate level.

Low-Temperature Chemical-Vapor-Deposition of Silicon-Nitride from Tetra-Silane and Hydrogen Azide

1992 ◽  
Vol 284 ◽  
Author(s):  
Ryoichi Ishihara ◽  
Hiroshi Kanoh ◽  
Yasutaka Uchida ◽  
Osamu Sugiura ◽  
Masakiyo Matsumura
Keyword(s):  
Chemical Vapor Deposition ◽  
Silicon Nitride ◽  
Vapor Deposition ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Atomic Ratio ◽  
Breakdown Field ◽  
Silicon Thin Film ◽  
Silicon Nitride Films ◽  
Low Field

ABSTRACTSilicon nitride films have been successfully deposited at a temperature as low as 300°C by chemical-vapor-deposition using tctra-silane (Si4 H10) and hydrogen azidc (HN3). Atomic ratio (N/Si) of the film deposited at 400°C was 1.47, i.e., the film was N-rich. Total hydrogen content was about 25atomic%. The breakdown-field strength was 6.5MV/cm at leakage-current density of 1μA/cm2, and the low-field resistivity was more than 1015 Ωcm. Similar electrical characteristics were obtained from films deposited at a temperature range between 300°C and 500°C. Amorphous silicon thin-film transistors equipped with this film as the gate dielectric showed good transfer characteristics.

Electrical Properties of Alkyl-Trichlorosilane Monolayers Grafted on Silicon Substrate

1993 ◽  
Vol 328 ◽  
Author(s):  
Dominique Vuillaume ◽  
Francis Rondelez
Keyword(s):  
Electrical Properties ◽  
Silicon Substrate ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Native Oxide ◽  
Breakdown Field ◽  
Organic Monolayer ◽  
Low Field ◽  
High Dielectric ◽  
Silicon Based

ABSTRACTWe demonstrate that a single monolayer of alkyl-trichlorosilane Molecules, covalently grafted to the native oxide of a silicon substrate, allows to fabricate silicon based MIS (Metal-Insulator-Semiconductor) devices with excellent electrical properties. The thickness of the organic monolayer is in the range 1.5–2.8 nm, corresponding to long alkyl chains with 8 to 18 carbon atoms. We have fabricated MIS capacitors with a leakage current density as low as 10-8 A/cm2 at 6 MV/cm, high dielectric breakdown field (12 MV/cm), electrically active defect density lower than 1011 cm-2, and low field dc conductivity as low as 10-16–10-15 Scm-1. Thermal stability has been demonstrated up to 450 °C.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Characterization of Oxide Etching and Wafer Cleaning using Vapor-Phase Anhydrous HF and Ozone

1997 ◽  
Vol 470 ◽  
Author(s):  
Barbara Froeschle ◽  
Lutz Deutschmann ◽  
Anton J. Bauer ◽  
Edmund P. Burte
Keyword(s):  
Vapor Phase ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Uv Light ◽  
Reference Sample ◽  
Surface Preparation ◽  
Time Dependent Dielectric Breakdown ◽  
Wafer Cleaning ◽  
Phase Surface ◽  
Cluster Tool

ABSTRACTA cleaning process using anhydrous HF (AHF)/methanol and ozone is carried out in a STEAG-AST Vapor Phase Cleaning module (VPC). This module is integrated in a state-of-the-art cluster tool also consisting of a STEAG-AST Rapid Thermal Oxidation module (RTO). The dependence of AHF vapor phase etch rate of thermally grown silicon dioxide on different process parameters, such as etch time, AHF-flow, and temperature is evaluated. The optimized etch process is found to be at a temperature of 40°C and at a pressure of 50 mbar for this VPC module. Using the above etch parameters various combinations of vapor phase surface preparation chemistries combining AHF etching and ozone/UV cleaning are evaluated.To demonstrate the feasibility of this cluster tool for advanced gate dielectric formation, 4.0 nm thin oxide is grown directly after the cleaning in the RTO module without breaking the vacuum. Time dependent dielectric breakdown results for oxides pre-oxidation-cleaned in AHF, and in AHF followed by ozone are compared to a reference sample without any dry pre-oxidation cleaning. It can be shown, that the cleaning in AHF with a subsequent ozone step at 200°C under UV light leads to improved breakdown characteristics compared to AHF/methanol cleanings without such subsequent ozone/UV step or conventional wet cleaning using HF-Dip.

Growth and Characterization of High-Performance GaN and AlxGa1−xN Ultraviolet Avalanche Photodiodes Grown on GaN Substrates

2007 ◽  
Vol 1040 ◽  
Author(s):  
Russell D. Dupuis ◽  
Dongwon Yoo ◽  
Jae-Hyun Ryou ◽  
Yun Zhang ◽  
Shyh-Chinag Shen ◽  
...  
Keyword(s):  
Defect Density ◽  
Growth Parameters ◽  
Avalanche Photodiodes ◽  
Chemical Vapor ◽  
Device Fabrication ◽  
Breakdown Field ◽  
Structural Quality ◽  
Epitaxial Layers ◽  
Free Standing

AbstractWide-bandgap III-nitride-based avalanche photodiodes (APDs) are important for photodetectors operating in UV spectral region. For the growth of GaN-based heteroepitaxial layers on lattice-mismatched substrates such as sapphire and SiC, a high density of defects is introduced, thereby causing device failure by premature microplasma breakdown before the electric field reaches the level of the bulk avalanche breakdown field, which has hampered the development of III-nitride based APDs. In this study, we investigate the growth and characterization of GaN and AlGaN-based APDs on free-standing bulk GaN substrates. Epitaxial layers of GaN and AlxGa1−xN p-i-n ultraviolet avalanche photodiodes were grown by metalorganic chemical vapor deposition (MOCVD). Improved crystalline and structural quality of epitaxial layers was achieved by employing optimum growth parameters on low-dislocation-density bulk substrates in order to minimize the defect density in epitaxially grown materials. GaN and AlGaN APDs were fabricated into 30μm- and 50μm-diameter circular mesas and the electrical and optoelectronic characteristics were measured. APD epitaxial structure and device design, material growth optimization, material characterizations, device fabrication, and device performance characteristics are reported.

Cleaning Process Optimization in a Gate Oxide Cluster Tool Using an in-Line XPS Module

1997 ◽  
Vol 477 ◽  
Author(s):  
Barbara Froeschle ◽  
Frédérique Glowacki ◽  
Anton J. Bauer ◽  
Igor Kasko ◽  
Richard Oechsner ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Uv Light ◽  
Reference Sample ◽  
Gate Oxide ◽  
Cleaning Process ◽  
Oxide Cluster ◽  
Time Dependent Dielectric Breakdown ◽  
Wafer Surfaces ◽  
Cluster Tool

ABSTRACTA cleaning process using anhydrous HF (AHF)/methanol and ozone was carried out in a STEAG AST Vapor Phase Cleaning module (VPC). This module was integrated in a state-of-theart cluster tool also consisting of a STEAG AST Rapid Thermal Oxidation module (RTO). To investigate the properties of silicon after cleaning a novel in-line XPS module was integrated into the gate oxide cluster. Measurements of fluorine, carbon, and oxygen contamination in the range from 0.01 to 1 monolayers on cleaned wafer surfaces and on regrown oxides (< 0.5 nm) have been performed and used for rapid optimization of the cleaning procedure. The in-line integration enabled measurements without exposing the wafers to atmosphere thus avoiding oxidation or contamination of the wafer surfaces. To demonstrate the feasibility of this cluster tool for advanced gate dielectric formation, 4.0 nm thin oxide was grown directly after the cleaning in the RTO module without breaking the vacuum. Time dependent dielectric breakdown results for oxides pre-oxidation-cleaned in AHF, and in AHF followed by ozone were compared to a reference sample without any dry pre-oxidation cleaning. It could be shown, that the cleaning in AHF with a subsequent ozone step at 200°C under UV light lead to improved breakdown characteristics compared to AHF/methanol cleanings without such subsequent ozone/UV step or conventional wet cleaning using HF-Dip.

Low-Temperature PECVD SiO2 On Si And SiC

1997 ◽  
Vol 483 ◽  
Author(s):  
L. Teng ◽  
W. A. Anderson
Keyword(s):  
Dielectric Constant ◽  
Leakage Current ◽  
Leakage Current Density ◽  
Current Density ◽  
Dielectric Breakdown ◽  
Growth Parameters ◽  
Chemical Vapor ◽  
Breakdown Field ◽  
Flat Band ◽  
Mos Capacitors

AbstractThe deposition of SiO2 films by plasma-enhanced-chemical-vapor-deposition (PECVD) using tetraethylorthosilicate (TEOS) was studied. MOS capacitors were fabricated on both Si and SiC for this study. Several different sets of experiments were conducted for PECVD deposition according to different growth parameters and the results compared. For Si samples with SiO2 deposited at a substrate temperature 300°C, the C∼V curve gave a flat-band voltage of 1V and a transition slope of 112 pF/V. The dielectric constant of the deposited SiO2 film was 4.2 and the Si/SiO2 interface trap density was calculated to be 1.8×1010 cm−2. The I-V curve showed a leakage current density of l.2×10−9 A/cm2 and dielectric breakdown field strength of 9.2 MV/cm. For SiC samples, the PECVD deposition gave a uniform SiO2 film with a controllable deposition rate of 0.3nm/sec. The refractive index and dielectric constant of the as-deposited SiO2 film were 1.46 and 3.84 respectively. The I∼V curve showed a leakage current density of 2×10−9 A/cm2 and a breakdown field of 4.7 MV/cm.

Improvement in Gate Dielectric Quality of Ultra Thin a: SiN:H MNS Capacitor by Hydrogen Etching of the Substrate

2002 ◽  
Vol 716 ◽  
Author(s):  
Parag C. Waghmare ◽  
Samadhan B. Patil ◽  
Rajiv O. Dusane ◽  
V.Ramgopal Rao
Keyword(s):  
Silicon Nitride ◽  
Gate Dielectric ◽  
Substrate Surface ◽  
Scaling Limit ◽  
Tunneling Current ◽  
Chemical Vapor ◽  
Poor Performance ◽  
State Density ◽  
Direct Tunneling Current

AbstractTo extend the scaling limit of thermal SiO2, in the ultra thin regime when the direct tunneling current becomes significant, members of our group embarked on a program to explore the potential of silicon nitride as an alternative gate dielectric. Silicon nitride can be deposited using several CVD methods and its properties significantly depend on the method of deposition. Although these CVD methods can give good physical properties, the electrical properties of devices made with CVD silicon nitride show very poor performance related to very poor interface, poor stability, presence of large quantity of bulk traps and high gate leakage current. We have employed the rather newly developed Hot Wire Chemical Vapor Deposition (HWCVD) technique to develop the a:SiN:H material. From the results of large number of optimization experiments we propose the atomic hydrogen of the substrate surface prior to deposition to improve the quality of gate dielectric. Our preliminary results of these efforts show a five times improvement in the fixed charges and interface state density.

Assessment of Reliability of cap layers used in Cu-Black DiamondTM Interconnects

2003 ◽  
Vol 766 ◽  
Author(s):  
Ahila Krishnamoorthy ◽  
N.Y. Huang ◽  
Shu-Yunn Chong
Keyword(s):  
Dielectric Layer ◽  
Dielectric Breakdown ◽  
Copper Ions ◽  
Dielectric Strength ◽  
Time Dependent ◽  
Breakdown Field ◽  
Field Range ◽  
Time Dependent Dielectric Breakdown ◽  
Voltage Ramp ◽  
Low K

AbstractBlack DiamondTM. (BD) is one of the primary candidates for use in copper-low k integration. Although BD is SiO2 based, it is vastly different from oxide in terms of dielectric strength and reliability. One of the main reliability concerns is the drift of copper ions under electric field to the surrounding dielectric layer and this is evaluated by voltage ramp (V-ramp) and time dependent dielectric breakdown (TDDB). Metal 1 and Metal 2 intralevel comb structures with different metal widths and spaces were chosen for dielectric breakdown studies. Breakdown field of individual test structures were obtained from V-ramp tests in the temperature range of 30 to 150°C. TDDB was performed in the field range 0.5 – 2 MV/cm. From the leakage between combs at the same level (either metal 1 or metal 2) Cu drift through SiC/BD or SiN/BD interface was characterized. It was found that Cu/barrier and barrier/low k interfaces functioned as easy paths for copper drift thereby shorting the lines. Cu/SiC was found to provide a better interface than Cu/SiN.

Nitrogen (N2) Implantation to Suppress Growth of Interfacial Oxide in Mocvd Bst and Sputtered Bst Films

1999 ◽  
Vol 567 ◽  
Author(s):  
Renee Nieh ◽  
Wen-Jie Qi ◽  
Yongjoo Jeon ◽  
Byoung Hun Lee ◽  
Aaron Lucas ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Nitrogen Concentration ◽  
Chemical Vapor ◽  
Future Generation ◽  
Oxide Thickness ◽  
Layer Growth ◽  
X Ray ◽  
Bst Films

ABSTRACTBa0.5Sr0.5TiO3 (BST) is one of the high-k candidates for replacing SiO2 as the gate dielectric in future generation devices. The biggest obstacle to scaling the equivalent oxide thickness (EOT) of BST is an interfacial layer, SixOy, which forms between BST and Si. Nitrogen (N2) implantation into the Si substrate has been proposed to reduce the growth of this interfacial layer. In this study, capacitors (Pt/BST/Si) were fabricated by depositing thin BST films (50Å) onto N2 implanted Si in order to evaluate the effects of implant dose and annealing conditions on EOT. It was found that N2 implantation reduced the EOT of RF magnetron sputtered and Metal Oxide Chemical Vapor Deposition (MOCVD) BST films by ∼20% and ∼33%, respectively. For sputtered BST, an implant dose of 1×1014cm−;2 provided sufficient nitrogen concentration without residual implant damage after annealing. X-ray photoelectron spectroscopy data confirmed that the reduction in EOT is due to a reduction in the interfacial layer growth. X-ray diffraction spectra revealed typical polycrystalline structure with (111) and (200) preferential orientations for both films. Leakage for these 50Å BST films is on the order of 10−8 to 10−5 A/cm2—lower than oxynitrides with comparable EOTs.

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