Cleaning Process Optimization in a Gate Oxide Cluster Tool Using an in-Line XPS Module

1997 ◽  
Vol 477 ◽  
Author(s):  
Barbara Froeschle ◽  
Frédérique Glowacki ◽  
Anton J. Bauer ◽  
Igor Kasko ◽  
Richard Oechsner ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Uv Light ◽  
Reference Sample ◽  
Gate Oxide ◽  
Cleaning Process ◽  
Oxide Cluster ◽  
Time Dependent Dielectric Breakdown ◽  
Wafer Surfaces ◽  
Cluster Tool

ABSTRACTA cleaning process using anhydrous HF (AHF)/methanol and ozone was carried out in a STEAG AST Vapor Phase Cleaning module (VPC). This module was integrated in a state-of-theart cluster tool also consisting of a STEAG AST Rapid Thermal Oxidation module (RTO). To investigate the properties of silicon after cleaning a novel in-line XPS module was integrated into the gate oxide cluster. Measurements of fluorine, carbon, and oxygen contamination in the range from 0.01 to 1 monolayers on cleaned wafer surfaces and on regrown oxides (< 0.5 nm) have been performed and used for rapid optimization of the cleaning procedure. The in-line integration enabled measurements without exposing the wafers to atmosphere thus avoiding oxidation or contamination of the wafer surfaces. To demonstrate the feasibility of this cluster tool for advanced gate dielectric formation, 4.0 nm thin oxide was grown directly after the cleaning in the RTO module without breaking the vacuum. Time dependent dielectric breakdown results for oxides pre-oxidation-cleaned in AHF, and in AHF followed by ozone were compared to a reference sample without any dry pre-oxidation cleaning. It could be shown, that the cleaning in AHF with a subsequent ozone step at 200°C under UV light lead to improved breakdown characteristics compared to AHF/methanol cleanings without such subsequent ozone/UV step or conventional wet cleaning using HF-Dip.

Characterization of Oxide Etching and Wafer Cleaning using Vapor-Phase Anhydrous HF and Ozone

1997 ◽  
Vol 470 ◽  
Author(s):  
Barbara Froeschle ◽  
Lutz Deutschmann ◽  
Anton J. Bauer ◽  
Edmund P. Burte
Keyword(s):  
Vapor Phase ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Uv Light ◽  
Reference Sample ◽  
Surface Preparation ◽  
Time Dependent Dielectric Breakdown ◽  
Wafer Cleaning ◽  
Phase Surface ◽  
Cluster Tool

ABSTRACTA cleaning process using anhydrous HF (AHF)/methanol and ozone is carried out in a STEAG-AST Vapor Phase Cleaning module (VPC). This module is integrated in a state-of-the-art cluster tool also consisting of a STEAG-AST Rapid Thermal Oxidation module (RTO). The dependence of AHF vapor phase etch rate of thermally grown silicon dioxide on different process parameters, such as etch time, AHF-flow, and temperature is evaluated. The optimized etch process is found to be at a temperature of 40°C and at a pressure of 50 mbar for this VPC module. Using the above etch parameters various combinations of vapor phase surface preparation chemistries combining AHF etching and ozone/UV cleaning are evaluated.To demonstrate the feasibility of this cluster tool for advanced gate dielectric formation, 4.0 nm thin oxide is grown directly after the cleaning in the RTO module without breaking the vacuum. Time dependent dielectric breakdown results for oxides pre-oxidation-cleaned in AHF, and in AHF followed by ozone are compared to a reference sample without any dry pre-oxidation cleaning. It can be shown, that the cleaning in AHF with a subsequent ozone step at 200°C under UV light leads to improved breakdown characteristics compared to AHF/methanol cleanings without such subsequent ozone/UV step or conventional wet cleaning using HF-Dip.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Study of Time Dependent Dielectric Breakdown Distribution in Ultrathin Gate Oxide

2007 ◽  
Vol 46 (No. 28) ◽  
pp. L691-L692 ◽  
Author(s):  
Takashi Miyakawa ◽  
Tsutomu Ichiki ◽  
Junichi Mitsuhashi ◽  
Kazutoshi Miyamoto ◽  
Tetsuo Tada ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Time Dependent ◽  
Time Dependent Dielectric Breakdown

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

Reliability and Ruggedness of Planar Silicon Carbide MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 782-787
Author(s):  
Kevin Matocha ◽  
In Hwan Ji ◽  
Sauvik Chowdhury
Keyword(s):  
Silicon Carbide ◽  
Threshold Voltage ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Time Dependent ◽  
Gate Bias ◽  
Constant Voltage ◽  
Time Dependent Dielectric Breakdown ◽  
Planar Silicon ◽  
State Of Art

The reliability and ruggedness of Monolith/Littelfuse planar SiC MOSFETs have been evaluated using constant voltage time-dependent dielectric breakdown for gate oxide wearout predictions, showing estimated > 100 year life at VGS=+25V and T=175C. Using extended time high-temperature gate bias, we have shown < 250 mV threshold voltage shifts for > 5000 hours under VGS=+25V and negligible threshold voltage shifts for > 2500 hours under VGS=-10V, both at T=175C. Under unclamped inductive switching, these 1200V, 80 mOhm SiC MOSFETs survive 1000 mJ of avalanche energy, meeting state-of-art ruggedness for 1200V SiC MOSFETs.

Reliability of 4H-SiC(000-1) MOS Gate Oxide Using N2O Nitridation

2009 ◽  
Vol 615-617 ◽  
pp. 557-560 ◽  
Author(s):  
Takuma Suzuki ◽  
Junji Senzaki ◽  
Tetsuo Hatakeyama ◽  
Kenji Fukuda ◽  
Takashi Shinohe ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Band Offset ◽  
Mos Capacitors ◽  
Conduction Band Offset ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability ◽  
Mos Gate

The oxide reliability of metal-oxide-semiconductor (MOS) capacitors on 4H-SiC(000-1) carbon face was investigated. The gate oxide was fabricated by using N2O nitridation. The effective conduction band offset (Ec) of MOS structure fabricated by N2O nitridation was increased to 2.2 eV compared with Ec = 1.7 eV for pyrogenic oxidation sample of. Furthermore, significant improvements in the oxide reliability were observed by time-dependent dielectric breakdown (TDDB) measurement. It is suggested that the N2O nitridation as a method of gate oxide fabrication satisfies oxide reliability on 4H-SiC(000-1) carbon face MOSFETs.

Effects of Silicon Ion Implantation upon Thin Gate Oxide Integrity

1992 ◽  
Vol 262 ◽  
Author(s):  
G. -S. Lee ◽  
J. -G. Park ◽  
S. -P. Choi ◽  
C. -H. Shin ◽  
Y. -B. Sun ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Surface Region ◽  
Gate Oxide ◽  
Near Surface ◽  
Time Dependent Dielectric Breakdown ◽  
Thin Gate Oxide ◽  
Si Ion Implantation ◽  
Gate Oxide Integrity

ABSTRACTIn this study, using oxide breakdown voltage and time-dependent-dielectric breakdown measurements, thermal wave modulated reflectance and chemical etching/optical microscopy, we investigated effects of Si ion implantation upon formation of D-defects and thin gate oxide integrity. Our data show that addition of Si ion implantation with a dose of up to 1013 ions/cm2 improves oxide integrity if the implantation is done at a certain step just before sacrificial oxidation in the Mb DRAM process. However, no improvement in oxide integrity is observed when the same implantation is done on the virgin wafer surfaces at the start of the same Mb DRAM process. We discuss our hypothesis that the improvement in oxide integrity is due to a reduction in the D-defect density in the near-surface region of the wafer.

Gate Oxide Reliability of SiC MOSFETs and Capacitors Fabricated on 150mm Wafers

2019 ◽  
Vol 963 ◽  
pp. 745-748 ◽  
Author(s):  
Daniel J. Lichtenwalner ◽  
Shadi Sabri ◽  
Edward van Brunt ◽  
Brett Hull ◽  
Satyaki Ganguly ◽  
...  
Keyword(s):  
Activation Energy ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Large Area ◽  
Temperature Dependent ◽  
Acceleration Parameter ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability ◽  
Voltage Breakdown ◽  
Linear Field

Gate oxide reliability on silicon carbide MOSFETs and large-area SiC N-type capacitors was studied for devices fabricated on 150mm SiC substrates. Oxide lifetime was measured under accelerated stress conditions using constant-voltage time-dependent dielectric breakdown (TDDB) testing, or ramped-voltage breakdown (RBD) testing. TDDB results from 1200V Gen3 MOSFETs reveal a field acceleration parameter of about 35 nm/V, similar to values reported for SiO2 on silicon. Temperature-dependent RBD tests of large capacitors from 25°C to 200°C reveal an apparent activation energy of 0.24eV, indicating that oxide lifetime increases as the temperature is decreased, as expected. Using this acceleration parameter and activation energy in the linear field model, the gate oxide lifetime from MOSFET TDDB testing extrapolates to greater than 108 hours at a gate voltage of 15 VGS at 175°C.

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