Electrical Properties of Alkyl-Trichlorosilane Monolayers Grafted on Silicon Substrate

1993 ◽  
Vol 328 ◽  
Author(s):  
Dominique Vuillaume ◽  
Francis Rondelez
Keyword(s):  
Electrical Properties ◽  
Silicon Substrate ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Native Oxide ◽  
Breakdown Field ◽  
Organic Monolayer ◽  
Low Field ◽  
High Dielectric ◽  
Silicon Based

ABSTRACTWe demonstrate that a single monolayer of alkyl-trichlorosilane Molecules, covalently grafted to the native oxide of a silicon substrate, allows to fabricate silicon based MIS (Metal-Insulator-Semiconductor) devices with excellent electrical properties. The thickness of the organic monolayer is in the range 1.5–2.8 nm, corresponding to long alkyl chains with 8 to 18 carbon atoms. We have fabricated MIS capacitors with a leakage current density as low as 10-8 A/cm2 at 6 MV/cm, high dielectric breakdown field (12 MV/cm), electrically active defect density lower than 1011 cm-2, and low field dc conductivity as low as 10-16–10-15 Scm-1. Thermal stability has been demonstrated up to 450 °C.

Gate Stack Formation using a Fully Integrated Single Wafer Cluster Tool

1997 ◽  
Vol 470 ◽  
Author(s):  
David C. Frystak ◽  
John Kuehne ◽  
Rick Wise ◽  
Burt Fowler ◽  
Phil Grothe ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Chemical Vapor ◽  
Breakdown Field ◽  
Fully Integrated ◽  
Low Field ◽  
Yield Values ◽  
Dielectric Charge ◽  
Cluster Tool

ABSTRACTA single wafer gate cluster tool has been evaluated in an effort to quantify the effects of gate clustering on defect density, process capability and device performance. The single wafer gate cluster tool consists of a hydrofluoric vapor (HF-vapor) pre-gate cleanup module, a rapid thermal oxidation (RTO) module and a polysilicon rapid thermal chemical vapor deposition (RTCVD) module. The gate dielectric charge to breakdown (Qbd) of capacitor structures formed using the integrated single wafer gate cluster tool process sequence typically averaged 9.1 to 12.3 coulombs per square centimeter (C/cm2). Excellent gate oxide integrity yield values in the range of 99.8% to 100% were also routinely obtained. The films were free of low field and mid field gate dielectric breakdown events and the devices exhibited dielectric breakdown field strength in excess of fourteen megavolts per centimeter (MV/cm). The cluster tool process was successfully integrated into a transistor device flow. The characteristics of devices formed using the cluster tool process were equivalent to those of devices formed using conventional batch processing at the gate level.

Study of SrTiO3 Gate Dielectrics

2006 ◽  
Vol 966 ◽  
Author(s):  
C.Y. Liu ◽  
Tseung-Yuen Tseng
Keyword(s):  
Dielectric Constant ◽  
Electrical Properties ◽  
Silicon Substrate ◽  
Interfacial Layer ◽  
High Dielectric Constant ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Measurement Techniques ◽  
High Quality ◽  
High Dielectric

ABSTRACTAmong various possible candidates of high-k gate dielectrics, SrTiO3 plays an important role because it has high dielectric constant and it can be epitaxially grown on silicon substrate. The fabrication process and properties of SrTiO3 gate dielectrics are reported. The effect of the addition of SiO2 on the microstructure and electrical properties of SrTiO3 gate dielectric is also presented. The minimization of the effect of interfacial layer between SrTiO3 and Si is the most important issue for obtaining high quality high-k gate dielectrics. The possible methods to improve the interfacial properties and the measurement techniques to characterize the interfacial layer are discussed.

Assessment of Reliability of cap layers used in Cu-Black DiamondTM Interconnects

2003 ◽  
Vol 766 ◽  
Author(s):  
Ahila Krishnamoorthy ◽  
N.Y. Huang ◽  
Shu-Yunn Chong
Keyword(s):  
Dielectric Layer ◽  
Dielectric Breakdown ◽  
Copper Ions ◽  
Dielectric Strength ◽  
Time Dependent ◽  
Breakdown Field ◽  
Field Range ◽  
Time Dependent Dielectric Breakdown ◽  
Voltage Ramp ◽  
Low K

AbstractBlack DiamondTM. (BD) is one of the primary candidates for use in copper-low k integration. Although BD is SiO2 based, it is vastly different from oxide in terms of dielectric strength and reliability. One of the main reliability concerns is the drift of copper ions under electric field to the surrounding dielectric layer and this is evaluated by voltage ramp (V-ramp) and time dependent dielectric breakdown (TDDB). Metal 1 and Metal 2 intralevel comb structures with different metal widths and spaces were chosen for dielectric breakdown studies. Breakdown field of individual test structures were obtained from V-ramp tests in the temperature range of 30 to 150°C. TDDB was performed in the field range 0.5 – 2 MV/cm. From the leakage between combs at the same level (either metal 1 or metal 2) Cu drift through SiC/BD or SiN/BD interface was characterized. It was found that Cu/barrier and barrier/low k interfaces functioned as easy paths for copper drift thereby shorting the lines. Cu/SiC was found to provide a better interface than Cu/SiN.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

scholarly journals Space Charge Characteristics and Electrical Properties of Micro-Nano ZnO/LDPE Composites

Crystals ◽  
2019 ◽  
Vol 9 (9) ◽  
pp. 481
Author(s):  
Jun-Guo Gao ◽  
Xia Li ◽  
Wen-Hua Yang ◽  
Xiao-Hong Zhang
Keyword(s):  
Electrical Properties ◽  
Space Charge ◽  
Synergistic Effects ◽  
Nano Particles ◽  
Breakdown Field ◽  
Nano Composite ◽  
Nano Zno ◽  
Additive Particles ◽  
Ldpe Composites ◽  
Short Connection

The synergistic effects of zinc oxide (ZnO) Micro/Nano particles simultaneously filled in low-density polyethylene (LDPE) on the space charge characteristics and electrical properties has been investigated by melt blending micro-scale and nanoscale ZnO additive particles into LDPE matrix to prepare Micro-ZnO, Nano-ZnO, and Micro-Nano ZnO/LDPE composites. The morphological structures of composite samples are characterized by Polarizing Light Microscopy (PLM), and the space charge accumulations and insulation performances are correlated in the analyses with Pulse Electronic Acoustic (PEA), DC breakdown field strength, and conductance tests. It is indicated that both the micro and nano ZnO fillers can introduce plenty of heterogeneous nuclei into the LDPE matrix so as to impede the LDPE spherocrystal growth and regularize the crystalline grains in neatly-arranged morphology. By filling microparticles together with nanoparticles of ZnO additives, the space charge accumulations are significantly inhibited under an applied DC voltage and the minimum initial residual charges with the slowest charge decaying rate have been achieved after an electrode short connection. While the micro-nano ZnO/LDPE composites acquire the lowest conductivity, the breakdown strengths of the ZnO/LDPE nanocomposite and micro-nano composite are, respectively, 13.7% and 3.4% higher than that of the neat LDPE material.

High Breakdown Field Dielectric Elastomer Actuators Using Encapsulated Polyaniline as High Dielectric Constant Filler

2010 ◽  
Vol 20 (19) ◽  
pp. 3280-3291 ◽  
Author(s):  
Martin Molberg ◽  
Daniel Crespy ◽  
Patrick Rupper ◽  
Frank Nüesch ◽  
Jan-Anders E. Månson ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
High Dielectric Constant ◽  
Dielectric Elastomer ◽  
Breakdown Field ◽  
Dielectric Elastomer Actuators ◽  
High Dielectric

scholarly journals STRUCTURAL AND ELECTRICAL PROPERTIES OF TANTALUM PENTAOXIDE (Ta2O5) THIN FILMS – A REVIEW

2013 ◽  
Vol 22 ◽  
pp. 564-569
Author(s):  
KANTA RATHEE ◽  
B. P. MALIK
Keyword(s):  
Thin Films ◽  
Dielectric Constant ◽  
Electrical Properties ◽  
Metal Oxide ◽  
High Dielectric Constant ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Structural And Electrical Properties ◽  
High Dielectric ◽  
Deposited Films

Down scaling of complementary metal oxide semiconductor transistors has put limitations on silicon dioxide to be used as an effective dielectric. It is necessary to replace the SiO 2 with a physically thicker layer of oxides of high dielectric constant. Thus high k dielectrics are used to suppress the existing challenges for CMOS scaling. Many new oxides are being evaluated as gate dielectrics such as Ta2O5 , HfO2 , ZrO2 , La2O3 , HfO2 , TiO2 , Al2O3 , Y2O3 etc but it was soon found that these oxides in many respects have inferior electronic properties to SiO2 . But the the choice alone of suitable metal oxide with high dielectric constant is not sufficient to overcome the scaling challenges. The various deposition techniques and the conditions under which the thin films are deposited plays important role in deciding the structural and electrical properties of the deposited films. This paper discusses in brief the various deposition conditions which are employed to improve the structural and electrical properties of the deposited films.

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