Effects of a Post-Emitter RTP on Bipolar NPN Beta Degradation Lifetime for 1.0 Micron & 0.8 Micron BICMOS Processes

1996 ◽  
Vol 429 ◽  
Author(s):  
W. E. Leitz ◽  
G. Modi ◽  
N. Parekh ◽  
E. Sabin ◽  
R. V. Taylor
Keyword(s):  
Thermal Processing ◽  
Reverse Bias ◽  
Rapid Thermal Processing ◽  
Electrical Performance ◽  
Current Gain ◽  
High Temperature Furnace ◽  
Performance Effects ◽  
Bicmos Process ◽  
Polysilicon Emitter ◽  
Temperature Furnace

AbstractRapid Thermal Processing (RTP) has sometimes been used to increase bipolar NPN Beta (Hfe, or current gain) for a polysilicon emitter BICMOS process. It has been demonstrated that Beta may be increased by 20%, compared to normal non-RTP process values, by the addition of an RTP cycle after the final high temperature furnace step. In our work it was found that emitter-base reverse bias degrades Beta much more severely for a process which uses RTP, than for a non-RTP process. In this paper we will report on the electrical performance effects of RTP on a variety of process parameters. The reliability effects on NPN Beta degradation lifetime, and NMOS reliability effects will be discussed as well.

Polysilicon Emitter Transistors Manufactured using a Novel Limited Reaction Processing System

1989 ◽  
Vol 146 ◽  
Author(s):  
Fred Ruddell ◽  
Colin Parkes ◽  
B Mervyn Armstrong ◽  
Harold S Gamble
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Processing System ◽  
Bipolar Transistors ◽  
Native Oxide ◽  
Plasma Oxidation ◽  
Oxide Removal ◽  
Polysilicon Emitter ◽  
Reaction Processing

ABSTRACTThis paper describes a LPCVD reactor which was developed for multiple sequential in-situ processing. The system is capable of rapid thermal processing in the presence of plasma stimulation and has been used for native oxide removal, plasma oxidation and silicon deposition. Polysilicon layers produced by the system are incorporated into N-P-N polysilicon emitter bipolar transistors. These devices fabricated using a sequential in-situ plasma clean-polysilicon deposition schedule exhibited uniform gains limited to that of long single crystal emitters. Devices with either plasma grown or native oxide layers below the polysilicon exhibited much higher gains. The suitability of the system for sequential and limited reaction processing has been established.

Diffusion Modeling of the Redistribution of Ion Implanted Impurities

1985 ◽  
Vol 52 ◽  
Author(s):  
Alwin E. Michel
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Device Fabrication ◽  
Diffusion Modeling ◽  
Enhanced Diffusion ◽  
The Common ◽  
Diffusion Mechanisms ◽  
Silicon Device ◽  
Temperature Furnace ◽  
Ion Implanted

ABSTRACTTransient enhanced diffusion during rapid thermal processing has been reported for most of the common dopants employed for silicon device fabrication. For arsenic a large amount of the available data is fit by a computational model based on accepted diffusion mechanisms. Ion implanted boron on the other hand exhibits anomalous tails and transient motiou. A time dependence of this displacement is demonstrated at lower temperatures. High temperature rapid anneals are shown to reduce some of the anomalous motion observed for low temperature furnace anneals. A model is described that links the electrical activation with the diffusion and describes both the transient diffusion of rapid thermal processing and the large anomalous diffusion reported many years ago for furnace anneals.

Control of Bipolar Junction Transistor Current Grain Using Rapid Thermal Processing.

1987 ◽  
Vol 92 ◽  
Author(s):  
A. Kermani ◽  
F. Van Gieson ◽  
S. Litwin ◽  
R. Sullivan ◽  
T. J. DeBolske ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Current Gain ◽  
Bipolar Junction Transistors ◽  
Electrical Characteristics ◽  
Bipolar Junction Transistor ◽  
Junction Transistor ◽  
The Common ◽  
Profile Technique ◽  
Better Than

ABSTRACTThe activation of ion implanted emitters for two types of NPN bipolar junction transistors ( BJT ) by rapid thermal processing (RTP) was evaluated. The dopant profiles and the resultant junction depths were measured for various thermal cycles, using spreading resistance profile technique. The electrical characteristics of the transistors were then determined and compared to the standard furnace processes. The common emitter current gain values, hFE, for arsenic emitters were low and phosphorous emitters exhibited improved or comparable betas. The breakdown voltages in common emitter configuration, BV,CEO, BVcEs and BVEBO were comparable or better than the furnace annealed samples and no evidence of transistor leakage was observed.

Ultra-Shallow Diffused Emitter-Base Profiles Fabricated by Rapid Thermal Processing for High Speed Bipolar Devices

1989 ◽  
Vol 146 ◽  
Author(s):  
J. E. Urner ◽  
C. I. Drowley ◽  
P. Vande Voorde ◽  
A. Kermani
Keyword(s):  
Thermal Processing ◽  
High Speed ◽  
Boron Concentration ◽  
Secondary Ion Mass Spectrometry ◽  
Rapid Thermal Processing ◽  
Depth Resolution ◽  
Device Fabrication ◽  
Bipolar Devices ◽  
Polysilicon Emitter ◽  
Secondary Ion

ABSTRACTThe development of next-generation high-speed bipolar devices depends critically on reproducible shallow dopant profiles, with base and emitter widths considerably less than 1000 Angstroms. Sequential diffusion of boron and arsenic from implanted polysilicon is a promising means of producing such shallow emitter-base profiles. The restricted thermal budget required to reproducibly form such shallow junctions severely limits the use of conventional furnaces. We report the formation of extremely shallow emitter-base profiles using rapid thermal processing (RTP) in a double-diffused polysilicon emitter process. Polysilicon was implanted with various doses of BF2 and subjected to a conventional furnace anneal at 900ºC. This process was followed by As implantation and furnace anneal at 900ºC or RTP at 10500C or 1100ºC. A range of emitter-base profiles was generated with emitter and base widths ranging from 350-800A. Emitter-base profiles were measured using low-energy Secondary Ion Mass Spectrometry (SIMS), after removal of the polysilicon to improve depth resolution. Deconvolution of the instrumental broadening function allowed extraction of base and emitter widths as well as the boron concentration in the base. Variation of the profiles is discussed as a function of anneal times and implant dose. Modified SUPREM III parameters are obtained for diffusivities under these RTP conditions. The implications for high speed bipolar device fabrication will be presented.

Point Defect Reaction in Silicon Wafers by Rapid Thermal Processing at More Than 1300°C Using an Oxidation Ambient

2019 ◽  
Vol 8 (1) ◽  
pp. P35-P40 ◽  
Author(s):  
Haruo Sudo ◽  
Kozo Nakamura ◽  
Susumu Maeda ◽  
Hideyuki Okamura ◽  
Koji Izunome ◽  
...  
Keyword(s):  
Point Defect ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Silicon Wafers ◽  
Defect Reaction

Modeling, Identification, and Control of Rapid Thermal Processing Systems

1994 ◽  
Vol 141 (11) ◽  
pp. 3200-3209 ◽  
Author(s):  
Charles D. Schaper ◽  
Mehrdad M. Moslehi ◽  
Krishna C. Saraswat ◽  
Thomas Kailath
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
And Control
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