Physics of Below Threshold Current Distribution in a-Si:H TFTs

1996 ◽  
Vol 424 ◽  
Author(s):  
H. C. Slade ◽  
M. S. Shur ◽  
S. C. Deane ◽  
M. Hack

AbstractWe have examined the material properties and operation of bottom-gate amorphous silicon thin film transistors (TFTs) using temperature measurements of the subthreshold current. From the derivative of current activation energy with respect to gate bias, we have deduced information about the density of states for several different transistor types. We have demonstrated that, in TFTs with thin active layers and top nitride passivation, the current conduction channel moves from the gate insulator interface to the passivation insulator interface as the transistor switches off. Our 2D simulations clarify these experimental results. We have examined the effect of bias stress on the transistors and analyzed the resulting reduction in the subthreshold slope. Based on these results, we have extended our analytic amorphous silicon TFI SPICE model to include the effect of bias stress.

1996 ◽  
Vol 420 ◽  
Author(s):  
H. C. Slade ◽  
M. S. Shur ◽  
S. C. Deane ◽  
M. Hack

AbstractWe have examined the material properties and operation of bottom-gate amorphous silicon thin film transistors (TFTs) using temperature measurements of the subthreshold current. From the derivative of current activation energy with respect to gate bias, we have deduced information about the density of states for several different transistor types. We have demonstrated that, in TFTs with thin active layers and top nitride passivation, the current conduction channel moves from the gate insulator interface to the passivation insulator interface as the transistor switches off. Our 2D simulations clarify these experimental results. We have examined the effect of bias stress on the transistors and analyzed the resulting reduction in the subthreshold slope. Based on these results, we have extended our analytic amorphous silicon TFT SPICE model to include the effect of bias stress.


1994 ◽  
Vol 336 ◽  
Author(s):  
H.S. Choi ◽  
Y.S. Kim ◽  
S.K. Lee ◽  
J.K. Yoon ◽  
W.S. Park ◽  
...  

ABSTRACTThe effects of top-insulator on the instability problems of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) have been studied. In a-Si:H TFT with top-insulator (E/S type), charge trapping into the both of top-insulator and gate insulator has been shown under the bias stress.In order to investigate the charge trapping effects of top-insulator, we proposed a new method of Measurement. By this Method, we observed that trapped charges in top-insulator increased drain currents for positive gate bias stress, and this increment of drain currents was more serious with increasing the ratio of source/drain overlap length to channel length. It has founded that the instability problems of a-Si:H TFTs was attributed to the effects of top-insulator as well as that of gate insulator.


1996 ◽  
Vol 424 ◽  
Author(s):  
Jeong Hyun Kim ◽  
Woong Sik Choi ◽  
Chan Hee Hong ◽  
Hoe Sup Soh

AbstractThe off current behavior of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) with an atmospheric pressure chemical vapor deposition (APCVD) silicon dioxide (SiO2) gate insulator were investigated at negative gate voltages. The a-Si:H TFT with SiO2 gate insulator has small off currents and large activation energy (Ea) of the off current compared to the a-Si:H TFT with SiNx gate insulator. The holes induced in the channel by negative gate voltage seem to be trapped in the defect states near the a-Si:H/SiO2 interface. The interface state density in the lower half of the band gap of a-Si:H/SiO2 appears to be much higher than that for a-Si:H/SiNx.


1999 ◽  
Vol 558 ◽  
Author(s):  
J.Y. Nahm ◽  
J.H. Lan ◽  
J. Kanicki

ABSTRACTA high-voltage hydrogenated amorphous silicon thin film transistor (H-V a-Si:H TFT) with thick double layer gate insulator (∼0.95 μm) has been developed for reflective active-matrix cholesteric liquid crystal displays. The double layer gate insulator consists of 0.85 and 0.10 μm thick benzocyclobutene and hydrogenated amorphous silicon nitride, respectively. This HV a-Si:H TFT operates at the gate-tosource and drain-to-source biases up to 100V without any serious leakage current degradation and device breakdown.


1990 ◽  
Vol 192 ◽  
Author(s):  
Tetsu Ogawa ◽  
Sadayoshi Hotta ◽  
Horoyoshi Takezawa

ABSTRACTThrough the time and temperature dependence measurements on threshold voltage shifts (Δ VT) in amorphous silicon thin film transistors, it has been found that two separate instability mechanisms exist; within short stress time ranges Δ Vτ increases as log t and this behavior corresponds to charge trapping in SiN. On the other hand, in long stress time ranges Δ VT increases as t t/4 and can be explained by time-dependent creation of trap in a-Si.


Sign in / Sign up

Export Citation Format

Share Document