3-Dimensional Integration Fabricated by Using Seeded Lateral Epitaxial Film on SiO2

1984 ◽  
Vol 33 ◽  
Author(s):  
N. Sasaki ◽  
T. Iwai ◽  
S. Kawamura ◽  
R. Mukai ◽  
K. Wada ◽  
...  

ABSTRACTSeeded lateral epitaxial laser-recrystallization of silicon film on SiO2 is applied to fabricate 3-dimensional (3-D) integrations: 3-D CMOS 7-stage ring oscillators. Top p-channel Si-gate SOI MOSFET's are fabricated in the seeded recrystallized silicon directly above bottom n-channel Si-gate bulk MOSFET's with insulator in between. The recrystallized silicon at the seed region can be utilized for buried contact to interconnect bottom and top MOSFET's. At the arsenic implantation step to fabricate source and drain of the bottom MOSFET's, ions are not implanted into the seed region to prevent heavy doping and crystal disorder there; otherwise the dopant diffuses laterally and residual crystal disorder disturbs the epitaxial recrystallization. After the laser-recrystallization, the seed region is implanted with phosphorus to interconnect the top and bottom MOSFET's.The Ar+ laser irradiation is performed with a 10 W power, a 50 μm spot size, a 13 cm/s scanning speed and a 13 μm step at 400 °C in air. Propagation delay of 460 psec is obtained for the seven stage 3-D CMOS ring oscillator at a power supply voltage of 17 V for a channel length of 3 μm and a channel width of 18 μm. In the seeded SOI films, grain boundary generation and crystal orientation can be controlled.

1984 ◽  
Vol 35 ◽  
Author(s):  
A.J. Auberton-Herve ◽  
J.P. Joly ◽  
J.M. Hode ◽  
J.C. Castagna

ABSTRACTSeeding from bulk silicon (lateral epitaxy) has been used in Ar+ laser recrystallization to achieve subboundary free silicon on insulator areas. On these areas C.MOS devices have been performed using almost entirely the standard processing steps of a bulk micronic C-MOS technology. n -MOS transistors with channel length as small as 0.3 um have shown very small leakage currents. This is attributed especially to the lack of subboundaries. A 40 % increase in the dynamic performances in comparison with equivalent size C-MOS bulk devices has been obtained (93 ps of delay time per stage for a 101 stages ring oscillator with 0.8 μm of channel length). This is the best result presented so far on recrystallized SOI. No special requirements are needed in the lay out of the circuit with the chosen seed structure. Furthermore an industrial processing rate for the laser recrystallization processing has been achieved using an elliptical laser beam, a high scan velocity (30 cm/s) and a 100 μm line to line scan step (a 4' wafer in 4 minutes).


Author(s):  
Masoud Soltani ◽  
Farzan Khatib ◽  
Seyyed Javad Seyyed Mahdavi Chabok

Purpose The purpose of this paper is to investigate a more robust ring oscillator. Less sensitivity to power supply variations is a target. This is important since low-quality ring oscillators could be exploited in numerous systems to reduce die costs. Design/methodology/approach The method in this work is large signal analysis. Delay time as the large signal parameter is calculated symbolically to explore dependency on a power supply voltage. Then simulations are performed to make a comparison. In this work, mathematical justifications are verified via HSPICE circuit simulator outputs, while 0.18 µm TSMC CMOS technology is exploited. Findings At least two combined configurations are presented with higher robustness. These circuits are more appropriate in noisy conditions. Both theoretical calculations and simulation results verify less sensitive oscillation against supply voltage ripples and temperature variations. Originality/value Introducing a band-switched inverter in combined configurations is contribution. In this way, three structures are presented which both show higher stability in oscillation frequency. The band switched delay time calculations are quite new and also the validity of the symbolical delay time approach is verified by circuit simulations.


Energies ◽  
2020 ◽  
Vol 13 (11) ◽  
pp. 2986 ◽  
Author(s):  
Ruhaifi Bin Abdullah Zawawi ◽  
Wajahat H. Abbasi ◽  
Seung-Hwan Kim ◽  
Hojong Choi ◽  
Jungsuk Kim

The robustness of the reference circuit in a wide range of supply voltages is crucial in implanted devices. Conventional reference circuits have demonstrated a weak performance over wide supply ranges. Channel-length modulation in the transistors causes the circuit to be sensitive to power supply variation. To solve this inherent problem, this paper proposes a new output-voltage-line-regulation controller circuit. When a variation occurs in the power supply, the controller promptly responds to the supply deviation and removes unwanted current in the output path of the reference circuit. The proposed circuit was implemented in a 0.35-μm SK Hynix CMOS standard process. The experimental results demonstrated that the proposed reference circuit could generate a reference voltage of 0.895 V under a power supply voltage of 3.3 V, line regulation of 1.85 mV/V in the supply range of 2.3 to 5 V, maximum power supply rejection ratio (PSRR) of −54 dB, and temperature coefficient of 11.9 ppm/°C in the temperature range of 25 to 100 °C.


2011 ◽  
Vol E94-C (6) ◽  
pp. 1072-1075
Author(s):  
Tadashi YASUFUKU ◽  
Yasumi NAKAMURA ◽  
Zhe PIAO ◽  
Makoto TAKAMIYA ◽  
Takayasu SAKURAI

2016 ◽  
Vol E99.C (10) ◽  
pp. 1219-1225
Author(s):  
Masahiro ISHIDA ◽  
Toru NAKURA ◽  
Takashi KUSAKA ◽  
Satoshi KOMATSU ◽  
Kunihiro ASADA

1993 ◽  
Vol 29 (15) ◽  
pp. 1324 ◽  
Author(s):  
L.E. Larson ◽  
M.M. Matloubian ◽  
J.J. Brown ◽  
A.S. Brown ◽  
M. Thompson ◽  
...  

2018 ◽  
Vol 27 (07) ◽  
pp. 1850116
Author(s):  
Yuanxin Bao ◽  
Wenyuan Li

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180[Formula: see text]nm CMOS process and occupies a small area of 0.048[Formula: see text]mm2 excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of [Formula: see text][Formula: see text]1.5[Formula: see text]C from [Formula: see text]45[Formula: see text]C to 85[Formula: see text]C under a supply voltage of 1.4–2.4[Formula: see text]V showing a worst-case supply sensitivity of 0.5[Formula: see text]C/V. The sensor maintains a high conversion rate of 45[Formula: see text]KS/s with a fine resolution of 0.25[Formula: see text]C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8[Formula: see text]V, the maximum energy consumption per conversion is only 7.8[Formula: see text]nJ at [Formula: see text]45[Formula: see text]C.


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