Rapid Thermal Crystallization Of LPCVD Amorphous Silicon Films

1994 ◽  
Vol 345 ◽  
Author(s):  
A. T. Voutsas ◽  
M. K. Hatalis ◽  
K. R. Olasupo ◽  
A. K. Nanda ◽  
D. Alugbin
Keyword(s):  
High Temperatures ◽  
Defect Density ◽  
Silicon Films ◽  
Electrical Characteristics ◽  
Rapid Thermal Anneal ◽  
Thermal Budget ◽  
Thermal Crystallization ◽  
High Annealing ◽  
Polysilicon Films ◽  
Crystalline Growth

AbstractThe crystallization of LPCVD a-Si by Rapid Thermal Anneal was investigated. RTA polysilicon films can find application in the fabrication of TFTs for AMLCDs, due to the lower thermal budget associated with fast crystallization at high temperatures. It was found that the grain size of the crystallized films decreases with the temperature, in the range of 700°C to 1100°C, while for higher temperatures the opposite trend is observed. The latter observation was attributed to the high thermal vibration of subcritical clusters, that was assumed responsible for the decline in the nuclei population at high annealing temperatures, combined with the faster crystalline growth rate at high temperatures. RTA silicon films were found to have lower intra-grain defect density, that may result in the improvement of the electrical characteristics of the polysilicon films.

Comparison of Structural and Electrical Characteristics of Solid-Phase Epitaxial Films Recrystallized By Rapid Thermal Annealing and Furnace Annealing

1985 ◽  
Vol 53 ◽  
Author(s):  
R. Sundaresan ◽  
P.-H. Chang ◽  
S.D.S. Malhi ◽  
H.W. Lam
Keyword(s):  
Solid Phase ◽  
Epitaxial Films ◽  
Electrical Characteristics ◽  
Lateral Extension ◽  
Rapid Thermal Anneal ◽  
Furnace Annealing ◽  
Layer 4 ◽  
Polysilicon Films ◽  
Average Electron ◽  
Temperature Furnace

ABSTRACTSolid-phase epitaxial regrowth of polysilicon films. amorphized by a room-temperature silicon implant. has been achieved using a (low temperature) furnace anneal or a (high temperature) rapid thermal anneal. Lateral extension of the growth onto an oxide layer, 4 μm wide, has also been observed. The electrical properties of the films were examined by building MO2S devices in them. Average electron mobilities of 520 cm2/v-sec and 200 cm2/v-sec have been measured for films regrown on top of silicon and oxide respectively.

A novel process for SiGe Core-Shell JAM Transistors Fabrication and thermal annealing effect on its electrical performance

2020 ◽  
Vol 1 (2) ◽  
Author(s):  
Ashish Kumar ◽  
Wen-Hsi Lee
Keyword(s):  
Process Condition ◽  
Subthreshold Swing ◽  
Electrical Performance ◽  
Core Shell ◽  
Electrical Characteristics ◽  
Thermal Budget ◽  
New Process ◽  
Comparable Performance ◽  
Higher Temperature ◽  
Film Annealing

 In this study, we fabricate Si/SiGe core-shell Junctionless accumulation mode (JAM)FinFET devices through a rapid and novel process with four main steps, i.e. e-beam lithography definition, sputter deposition, alloy combination annealing, and chemical solution etching. The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm. After finishing the fabrication of devices, we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch. A poly-Si/SiGe core -shell JAMFETs was successfully demonstrated and it also exhibits  a superior subthreshold swing of 81mV/dec and high on/off ratio > 105 when annealing for 1hr at 600°C. The thermal diffusion process condition for this study are 1hr at 600°C and 6hr at 700°C for comparison. The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other. Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film. Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e. at higher temperature. This new process can still fabricate a comparable performance to classical planar FinFET in driving current. 

Phonon Conduction Normal to Polysilicon Films on Diamond

2013 ◽  
Author(s):  
Jungwan Cho ◽  
Pane C. Chao ◽  
Mehdi Asheghi ◽  
Kenneth E. Goodson
Keyword(s):  
Thermal Conductivity ◽  
Transport Theory ◽  
Phonon Scattering ◽  
Phonon Transport ◽  
Silicon Films ◽  
Silicon Thin Films ◽  
Transmission Electron ◽  
Crystal Films ◽  
Polysilicon Films ◽  
Polycrystalline Silicon Films

Silicon films of thickness near and below one micrometer play a central role in many advanced technologies for computation and energy conversion. Numerous data on the thermal conductivity of silicon thin films are available in the literature, but mainly for the in-plane thermal conductivity of polycrystalline and single-crystal films. Here we use picosecond time-domain thermoreflectance (TDTR), transmission electron microscopy, and phonon transport theory to investigate heat conduction normal to polycrystalline silicon films on diamond substrates. The data agree with predictions that account for the coupled effects of phonon scattering on film boundaries and defects concentrated near grain boundaries. Using the data and the model, we estimate the polysilicon-diamond interface resistance to be 6.5–8 m2 K GW−1.

On the relation between defect density and dopant concentration in amorphous silicon films

2000 ◽  
Vol 266-269 ◽  
pp. 565-568 ◽  
Author(s):  
Domenico Caputo ◽  
Giampiero de Cesare ◽  
Fernanda Irrera ◽  
Augusto Nascetti ◽  
Fabrizio Palma
Keyword(s):  
Amorphous Silicon ◽  
Dopant Concentration ◽  
Defect Density ◽  
Silicon Films

Ultra-Shallow P+/N Junctions Formed by SiF4 Preamorphization and BF3 Implantation Using Plasma Immersion Ion Implantation

1992 ◽  
Vol 279 ◽  
Author(s):  
Erin C. Jones ◽  
Seongil Im ◽  
Nathan W. Cheung
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Ion Implantation ◽  
Amorphous Region ◽  
Electrical Characteristics ◽  
Applied Bias ◽  
Rapid Thermal Anneal ◽  
Transmission Electron ◽  
Plasma Immersion Ion Implantation ◽  
Si Wafer

ABSTRACTSub-100 nm P+/N junctions are fabricated by implanting wafers in the plasma immersion ion implantation system (PIII). Ions from SiF4 and BF3 plasmas are implanted at energies from 4–6 keV and 2 keV, respectively. The amorphous region formed by SiF4 im-plantion is shown to be effective in slowing B diffusion during a 10 sec, 1060°C rapid thermal anneal step. Channeling and transmission electron microscopy studies show the recrys-tallized amorphous region is comparable in quality to an unprocessed Si wafer, and the implantation and annealing sequence has no detrimental effects on the physical or electrical characteristics of fabricated devices. Diodes have forward ideality factors of 1.05 to 1.06 and reverse leakage as low as 2 nA/cm2 in the diode bulk at -5 V applied bias.

Selective Nickel Silicide Wet Etchback Chemistry for Low Temperature Anneal Process

2012 ◽  
Vol 195 ◽  
pp. 37-41
Author(s):  
Tan Yong Siang ◽  
Seah Boon Meng ◽  
Leong Lup San ◽  
Liu Huang ◽  
Zainab Ismail ◽  
...  
Keyword(s):  
Low Temperature ◽  
Lateral Diffusion ◽  
Nickel Silicide ◽  
Wet Etching ◽  
Formation Temperature ◽  
Rapid Thermal Anneal ◽  
Thermal Budget ◽  
Silicide Layer ◽  
Metal Silicides ◽  
Technology Nodes

The salicide (self-aligned silicide) technology involves selective wet etching step of non-reacted metal with respect to metal silicides. It was introduced in MOSFET fabrication due to the increase of the source, drain and gate resistances with the reduction of device dimensions. The introduction of a low resistive silicide layer on these areas has become mandatory to meet device specifications. NiSi has been widely considered for sub-65nm technology nodes due to its low resistivity, low silicon consumption and low formation temperature [1-2]. The two step annealing sequence is common in the industry for nickel silicide application to control the reverse linewidth effect. However, since Ni is the diffusing element in the NiSi reaction, a first high temperature rapid thermal anneal (RTA) will inadvertently result in Ni lateral diffusion under the spacer towards the gate causing electrical shorts. Indeed, a first low temperature anneal could seriously limit the nickel lateral diffusion and prevent this phenomenon. Minimizing thermal budget by means of reducing the temperature has also been proven to lower junction leakage current [3].

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