Process Integration and Manufacturasility Issues for High Performance Multilevel Interconnect

1994 ◽  
Vol 337 ◽  
Author(s):  
Shin-Puu Jeng ◽  
Robert H. Havemann ◽  
Mi-Chang Chang
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Dielectric Materials ◽  
Deep Submicron ◽  
Limiting Factor ◽  
Feature Size ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Improved Performance ◽  
On Chip

ABSTRACTInterconnect delay is shown to be a performance-limiting factor for ULSI circuits when feature size is scaled into the deep submicron region, due to a rapid increase in interconnect resistivity and capacitance. Dielectric materials with lower values of permittivity are needed to reduce the line-to-line capacitance as metal spacing decreases. However, the challenge is to successfully integrate these materials into on-chip interconnects. A new multilevel interconnect scheme has been developed that gives improved performance through insertion of a low-dielectric-constant material between metal leads. A novel polymer/Si02 composite dielectric structure provides lower line-to-line capacitance while alleviating many of the integration and reliability problems associated with polymers in standard interconnect processing.

Overview Of Process Integration Issues For Low K Dielectrics

1998 ◽  
Vol 511 ◽  
Author(s):  
R. H. Havemann ◽  
M. K. Jain ◽  
R. S. List ◽  
A. R. Ralston ◽  
W-Y. Shih ◽  
...  
Keyword(s):  
Large Scale ◽  
Process Integration ◽  
Functional Integration ◽  
Dielectric Materials ◽  
Limiting Factor ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Rc Delay ◽  
Low K

ABSTRACTThe era of silicon Ultra-Large-Scale-Integration (ULSI) has spurred an everincreasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. Both interconnect resistance and capacitance play key roles in overall performance, but modeling simulations have highlighted the importance of reducing parasitic capacitance to manage crosstalk, power dissipation and RC delay. New dielectric materials with lower permittivity (k) are needed to meet this challenge. This paper summarizes the process integration and reliability issues associated with the use of novel low k materials in multilevel interconnects.

scholarly journals Network-On-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction

2021 ◽  
Author(s):  
Isiaka A. Alimi ◽  
Romil K. Patel ◽  
Oluyomi Aboderin ◽  
Abdelgader M. Abdalla ◽  
Ramoni A. Gbadamosi ◽  
...  
Keyword(s):  
High Performance ◽  
Research Direction ◽  
Network On Chip ◽  
Limiting Factor ◽  
Single Chip ◽  
Chip Design ◽  
Application Mapping ◽  
Technology Advancement ◽  
On Chip ◽  
Heterogeneous Cores

Integration technology advancement has impacted the System-on-Chip (SoC) in which heterogeneous cores are supported on a single chip. Based on the huge amount of supported heterogeneous cores, efficient communication between the associated processors has to be considered at all levels of the system design to ensure global interconnection. This can be achieved through a design-friendly, flexible, scalable, and high-performance interconnection architecture. It is noteworthy that the interconnections between multiple cores on a chip present a considerable influence on the performance and communication of the chip design regarding the throughput, end-to-end delay, and packets loss ratio. Although hierarchical architectures have addressed the majority of the associated challenges of the traditional interconnection techniques, the main limiting factor is scalability. Network-on-Chip (NoC) has been presented as a scalable and well-structured alternative solution that is capable of addressing communication issues in the on-chip systems. In this context, several NoC topologies have been presented to support various routing techniques and attend to different chip architectural requirements. This book chapter reviews some of the existing NoC topologies and their associated characteristics. Also, application mapping algorithms and some key challenges of NoC are considered.

Methods And Needs For Low K Material Research

1995 ◽  
Vol 381 ◽  
Author(s):  
Chiu H. Ting ◽  
Thomas E. Seidel
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Material Research ◽  
Material Development ◽  
Device Reliability ◽  
New Material ◽  
Speed Up ◽  
Low K

AbstractFor several years the industry has recognized the need of developing low k dielectric material and high conductivity metal for high performance interconnect. Low k dielectric will impact both power and delay favorably, while higher conductivity metal will reduce delay time. In order to be useful, new low k dielectric materials must be carefully characterized for their electrical, chemical, thermal and mechanical properties. In addition, their impact on process integration, fabrication cost and device reliability must also be considered. Since the gestation period for introducing a new material is very long, a set of standard testing methodologies are required to speed up the development process. This review will discuss various material options and the progress of material development and characterization methodologies. Example results will be provided for assessing these parameters.

Process Integration issues for Interlevel Dielectric Materials for Sub-quarter Micron Silicon Integrated Circuits

1998 ◽  
Vol 511 ◽  
Author(s):  
Vijay Parihar ◽  
R. Singh
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Process Integration ◽  
Dielectric Materials ◽  
New Approach ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Silicon Integrated Circuits ◽  
Processing Techniques ◽  
Low K

ABSTRACTThe continued miniaturization towards sub-quarter micron feature size mandates the search for low dielectric constant interlayer dielectric materials. A large number of materials and processing techniques has been suggested, but so far none of the proposed dielectric materials as well as processing techniques have been integrated into standard integrated circuit processing. In this paper, a new approach has been formulated for integration of low-k dielectric materials for future integrated circuits.

Enhancing dielectric and mechanical properties of poly(arylene ether nitrile) based composites by introducing low content “core-shell” like structured MXene&PDA@ BaTiO3

2021 ◽  
pp. 095400832110149
Author(s):  
Weixi Zhang ◽  
Yuan Kai ◽  
Jian Lin ◽  
Yumin Huang ◽  
Xiaobo Liu
Keyword(s):  
Dielectric Properties ◽  
Photoelectron Spectroscopy ◽  
High Performance ◽  
Composite Films ◽  
Dielectric Materials ◽  
Nanocomposite Films ◽  
Core Shell ◽  
Low Dielectric ◽  
The Fourier Transform ◽  
High Dielectric

Polyarylene ether nitrile (PEN) based composites combined MXene, Polydopamine (PDA) and barium titanate (BaTiO3, BT) with “core-shell”-like structure were developed successfully in this work, and then incorporating into the PEN matrix to form the PEN/MXene&PDA@BT nanocomposite films through the solution casting method. The novel MXene&PDA@BT nanoparticles were characterized by the Fourier transform infrared spectroscopy (FT-IR), thermogravimetric analysis (TGA), X-ray photoelectron spectroscopy (XPS), and scanning electron microscopy (SEM). Then the structure and properties of the obtained PEN/MXene&PDA@BT nanocomposites are studied in detail. The results show that the modification of PDA improved the dispersibility of MXene nanosheets and BT nanoparticles in the PEN matrix, resulting in the enhancement of mechanical and dielectric properties. The research results reveal that when the content of MXene&PDA@BT is 1%, the tensile strength and modulus reached 114.15 MPa and 3015.74 MPa, respectively. Most important, the PEN based nanocomposites exhibit the outstanding frequency in dependent dielectric properties, including high dielectric constant (5.08 at 1 kHz) and low dielectric loss (0.0178 at 1 kHz). These results indicate that the PEN/MXene&PDA@BT composite films are greatly significant for using as the constructing high performance dielectric materials.

Thermal-Aware SoC Test Scheduling

2011 ◽  
pp. 413-433 ◽  
Author(s):  
Zhiyuan He ◽  
Zebo Peng ◽  
Petru Eles
Keyword(s):  
High Performance ◽  
Deep Submicron ◽  
Test Time ◽  
Test Scheduling ◽  
Cooling Period ◽  
Time Minimization ◽  
Partition Test ◽  
Alternative Test ◽  
Test Sets ◽  
On Chip

High temperature has become a technological barrier to the testing of high performance systems-on-chip, especially when deep submicron technologies are employed. In order to reduce test time while keeping the temperature of the cores under test within a safe range, thermal-aware test scheduling techniques are required. In this chapter, the authors address the test time minimization problem as how to generate the shortest test schedule such that the temperature limits of individual cores and the limit on the test-bus bandwidth are satisfied. In order to avoid overheating during the test, the authors partition test sets into shorter test sub-sequences and add cooling periods in between, such that applying a test sub-sequence will not drive the core temperature going beyond the limit. Furthermore, based on the test partitioning scheme, the authors interleave the test sub-sequences from different test sets in such a manner that a cooling period reserved for one core is utilized for the test transportation and application of another core. The authors have proposed an approach to minimize the test application time by exploring alternative test partitioning and interleaving schemes with variable length of test sub-sequences and cooling periods as well as alternative test schedules. Experimental results have shown the efficiency of the proposed approach.

scholarly journals Cosimulation of Power and Temperature Models at the SystemC/TLM for a Soft-Core Processor

2020 ◽  
Vol 2020 ◽  
pp. 1-7
Author(s):  
Zineb El Hariti ◽  
Abdelhakim Alali ◽  
Mohamed Sadik ◽  
Kaoutar Aamali
Keyword(s):  
High Performance ◽  
System Level ◽  
Limiting Factor ◽  
Power Budget ◽  
Technology Roadmap ◽  
Systems On Chip ◽  
Limited Power ◽  
Virtual Platform ◽  
On Chip ◽  
Technology Nodes

Nowadays, modern embedded applications are becoming more and more complex and resource demanding. Fortunately, Systems on Chip (SoC) are one of the keys used to follow their requirements that stand in need of high performance while maintaining a low-power profile. On one hand, today, due to the limited power budget imposed by the batteries, power is the limiting factor of the logic CMOS. On the other hand, the downscaling of the technology node for 65 nm and beyond, based on the International Technology Roadmap for Semiconductors (ITRS) as a reference, has not only resulted in huge energy consumption but also increased the temperature chip. To address this challenge, designing at the system level is the suitable measure to tackle with the complexity of the Systems on Chip, aiming at having better adjustment between timing and accuracy for power and temperature estimations. We present in this paper, at the first stage, two models describing the static and dynamic power at the physical level. These models are implemented on an open virtual platform Model Power-Consumption and Temperature in SystemC/TLM (LIBTLMPWT) based on a representative SoC architecture. At the second stage, we focus on power, especially the thermal behaviour of the chip while running three benchmarks set on the game of life application for two different technology nodes.

Low Power Aging-Aware On-Chip Memory Structure Design by Duty Cycle Balancing

2016 ◽  
Vol 25 (09) ◽  
pp. 1650115
Author(s):  
Shuai Wang ◽  
Tao Jin ◽  
Chuanlei Zheng ◽  
Guangshan Duan
Keyword(s):  
Low Power ◽  
Duty Cycle ◽  
High Performance ◽  
Power Saving ◽  
Deep Submicron ◽  
Structure Design ◽  
Aging Effects ◽  
Register Files ◽  
On Chip ◽  
Memory Structures

The degradation of CMOS devices over the lifetime can cause severe threat to the system performance and reliability at deep submicron semiconductor technologies. The negative bias temperature instability (NBTI) is among the most important sources of the aging mechanisms. Applying the traditional guardbanding technique to address the decreased speed of devices is too costly. On-chip memory structures, such as register files and on-chip caches, suffer a very high NBTI stress. In this paper, we propose the aging-aware design to combat the NBTI-induced aging in integer register files, data caches and instruction caches in high-performance microprocessors. The proposed aging-aware design can mitigate the negative aging effects by balancing the duty cycle ratio of the internal bits in on-chip memory structures. Besides the aging problem, the power consumption is also one of the most prominent issues in microprocessor design. Therefore, we further propose to apply the low power schemes to different memory structures under aging-aware design. The proposed low power aging-aware design can also achieve a significant power reduction, which will further reduce the temperature and NBTI degradation of the on-chip memory structures. Our experimental results show that our aging-aware design can effectively reduce the NBTI stress with 30.8%, 64.5% and 72.0% power saving for the integer register file, data cache and instruction cache, respectively.

Reliability and Copper Interconnections with Low Dielectric Constant Materials

1998 ◽  
Vol 511 ◽  
Author(s):  
C-K. Hu
Keyword(s):  
Process Integration ◽  
Low Dielectric Constant ◽  
Adhesion Barrier ◽  
Low Dielectric ◽  
Low Dielectric Constant Materials ◽  
Electromigration Lifetime ◽  
The Difference ◽  
On Chip ◽  
Metal Liner ◽  
Interconnect Systems

ABSTRACTThe materials, process integration, and reliability issues in the development of multilevel electroplated Cu/polyimide on-chip interconnections are described. A combination of: good diffusion/adhesion barrier layers consisting of a metal liner plus the insulator Si3N4, and W stud/Si contacts resulted in a highly reliable IC chip. Electromigration of Cu damascene lines in both SiO2 and polyimide structures was investigated. Similar void growth was observed at the cathode ends of both the interconnect systems. However, the shapes of protrusions at the anode ends of the lines were different. Although the activation energies for both near bamboo-like Cu/SiO2 and Cu/polyimide were both 1.1 eV, the electromigration lifetime of the former was significantly longer. The difference is largely attributable to the poorer thermal conductivity of polyimide.

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