Silicided P-N Junction Diodes Fabricated by Silicidation through Silicon Buffer Layer and Dopant Drive-Out Process

1993 ◽  
Vol 320 ◽  
Author(s):  
W. M. Chen ◽  
J. C. Lee ◽  
M.R. Frost

ABSTRACTThis study investigates characteristics of p-n junction diodes fabricated by silicidation through a silicon buffer layer and dopant drive-out process. The purpose of using the buffer silicon layer is to reduce silicon consumption from the Si substrate during silicidation, and thus reduce the effective junction depth. The resulting structure is suitable for elevated CoSi2 source/drain contact in a metal-oxide-semiconductor field effect transistor or a silicided polysilicon emitter in a bipolar junction transistor. It was found that boron diffusion is enhanced by these buffer layers comparing to silicided diodes without silicon buffer layers. The sheet resistance of the CoSi2/polysilicon/Si structure does not degrade as seriously as CoSi2/polysilicon/oxide structure. The diode leakage current density is higher compared to diodes without buffer layers, especially when thinner buffer layers and high temperature 1000°C anneal are used.

2000 ◽  
Vol 623 ◽  
Author(s):  
Joo Dong Park ◽  
Tae Sung Oh

AbstractPt/SBT/TiO2/Si structure was proposed for metal/ferroelectric/insulator/semiconductor field effect transistor (MFIS-FET) applications. SrBi2.4 Ta2O9 (SBT) thin films of 400 nm thickness were prepared using liquid source misted chemical deposition (LSMCD) on Si(100) substrates with TiO2 buffer layers deposited by DC reactive sputtering with the thickness ranging from 5 nm to 200 nm and electrical properties of MFIS structures were investigated. Memory window and maximum capacitance of the Pt/SBT/TiO2 /Si structure increased with decreasing the thickness of TiO2 buffer layer. The Pt/SBT(400 nm)/TiO2(10 nm)/Si structure exhibited C-V hysteresis loop with the memory window of 1.6 V at ±5 V, and could be applicable for MFISFET applications.


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