Electrical Characteristics of LSMCD-Derived SrBi2.4Ta2O9 Thin Films Using TiO2 Buffer Layer for Metal/Ferroelectric/Insulator/Semiconductor Field Effect Transistor Devices

Pt/SBT/TiO2/Si structure was proposed for metal/ferroelectric/insulator/semiconductor field effect transistor (MFIS-FET) applications. SrBi2.4 Ta2O9 (SBT) thin films of 400 nm thickness were prepared using liquid source misted chemical deposition (LSMCD) on Si(100) substrates with TiO2 buffer layers deposited by DC reactive sputtering with the thickness ranging from 5 nm to 200 nm and electrical properties of MFIS structures were investigated. Memory window and maximum capacitance of the Pt/SBT/TiO2 /Si structure increased with decreasing the thickness of TiO2 buffer layer. The Pt/SBT(400 nm)/TiO2(10 nm)/Si structure exhibited C-V hysteresis loop with the memory window of 1.6 V at ±5 V, and could be applicable for MFISFET applications.