Ti/Pt Based Contacts to Heterojunction Bipolar Transistors

1992 ◽  
Vol 260 ◽  
Author(s):  
T. S. Kalkur ◽  
P. D. Wright ◽  
S. K. Ko ◽  
Y. C. Lu ◽  
L. Casas ◽  
...  

ABSTRACTTi/Pt metallization was used to form contacts on both n+-InAs emitter cap and p+ base layers of heterojunction bipolar transistors (HBTs). The as-deposited contacts were found to be ohmic for both the base and emitter cap layers. Rapid thermal processing of the contact metallizations was performed in the temperature range of 3 00–500 C for 30 seconds. Minimum contact resistivities of l×10-6 ohm-cm2 for the base and 3×l0-7 ohm-cm2 for the emitter layer were achieved. The influence of heat treatment on contact morphology was also examined.

1991 ◽  
Vol 241 ◽  
Author(s):  
R. A. Metzger ◽  
A. S. Brown ◽  
R. G. Wilson ◽  
T. Liu ◽  
W. E. Stanchina ◽  
...  

ABSTRACTAlInAs and GaInAs lattice matched to InP and grown by MBE over a temperature range of 200 to 350°C (normal growth temperature of 500°C) has been used to enhance the device performance of inverted (where the donor layer lies below the channel) High Electron Mobility Transistors (HEMTs) and Heterojunction Bipolar Transistors (HBTs), respectively. We will show that an AlInAs spacer grown over a temperature range of 300 to 350°C and inserted between the AlInAs donor layer and GaInAs channel significantly reduces Si movement from the donor layer into the channel. This produces an inverted HEMT with a channel charge of 3.0×1012 cm−2 and mobility of 9131 cm2/V-s, as compared to the same HEMT with a spacer grown at 500 °C resulting in a channel charge of 2.3×1012 cm−2 and mobility of 4655 cm2/V-s. We will also show that a GaInAs spacer grown over a temperature range of 300 to 350°C and inserted between the AlInAs emitter and GalnAs base of an npn HBT significantly reduces Be movement from the base into the emitter, thereby allowing higher Be base dopings (up to 1×1020 cm−3) confined to 500 Å base widths, resulting in an AlInAs/GaInAs HBT with an fmax of 73 GHz and ft of 110 GHz.


1989 ◽  
Vol 146 ◽  
Author(s):  
Fred Ruddell ◽  
Colin Parkes ◽  
B Mervyn Armstrong ◽  
Harold S Gamble

ABSTRACTThis paper describes a LPCVD reactor which was developed for multiple sequential in-situ processing. The system is capable of rapid thermal processing in the presence of plasma stimulation and has been used for native oxide removal, plasma oxidation and silicon deposition. Polysilicon layers produced by the system are incorporated into N-P-N polysilicon emitter bipolar transistors. These devices fabricated using a sequential in-situ plasma clean-polysilicon deposition schedule exhibited uniform gains limited to that of long single crystal emitters. Devices with either plasma grown or native oxide layers below the polysilicon exhibited much higher gains. The suitability of the system for sequential and limited reaction processing has been established.


1991 ◽  
Vol 240 ◽  
Author(s):  
Bernard M. Henry ◽  
A. E. Staton-Bevan ◽  
V. K. M. Sharma ◽  
M. A. Crouch ◽  
S. S. Gill

ABSTRACTAu/Pd/Ti and Au/Ti/Pd ohmic structures to thin p+-GaAs layers have been investigated for use as contacts to the base region of HJBTs. The Au/Pd/Ti contact system yielded specific contact resistivities at or above 2.8 × 10−5Ω:cm2. Heat treatments up to 8 minutes at 380°C caused only limited interaction between the metallization and the semiconductor. The metal penetrated to a maximum depth of ≃2nm. Specific contact resistivity values less than 10−5Ωcm2 were achieved using the Au/Ti/Pd (400/75/75nm) scheme. The nonalloyed Au/Ti/Pd contact showed the best combination of electrical and structural properties with a contact resistivity value of 9 × 10≃6Ωcm2 and Pd penetration of the GaAs epilayer to a depth of cs30nm.


1987 ◽  
Vol 92 ◽  
Author(s):  
R. S. Hockett

ABSTRACTRapid Thermal Processing is being evaluated in the IC industry as a way to meet the thermal budget requirements of reduced scaling in high performance Si IC's. As scaling is reduced and alternative processing is used, the study of low level interfacial impurities is expected to become more important. An example is presented here for the redistribution of interfacial impurities under RTP for polysilicon capped silicon similar to that proposed for shallow junction bipolar transistors.


1994 ◽  
Vol 136 (1-4) ◽  
pp. 230-234 ◽  
Author(s):  
W.T. Moore ◽  
A.J. SpringThorpe ◽  
T.P. Lester ◽  
S. Eicher ◽  
R.K. Surridge ◽  
...  

1986 ◽  
Vol 74 ◽  
Author(s):  
S. J. Pennycook ◽  
R. J. Culbertson

AbstractWe report the transient enhanced diffusion of supersaturated phosphorus in ion-implanted SPE grown Si. Precipitation proceeds rapidly to a metastable SiP phase, which can be converted to an orthorhombic form or redissolved by subsequent heat treatment. The effects are strongly temperature dependent, and consistent with the trapped interstitial model. The behavior of different dopants follows their relative interstitialcy diffusion coefficients. The results suggest that ion implantation induced point defects dominate over thermally activated point defects during low temperature and certain rapid thermal processing, controlling dopant deactivation and diffusion in crystalline or amorphous silicon, and can also affect the SPE growth rate.


1999 ◽  
Vol 14 (5) ◽  
pp. 1939-1943 ◽  
Author(s):  
Wen-yi Lin ◽  
Robert F. Speyer

Rapid thermal processing of BaTiO3 and TiO2 pressed powders at 500 °C/min to 1250 °C for 2 h in an infrared furnace resulted in a mixture of Ba2Ti9O20, BaTi4O9, and TiO2. Further heat treatment at 1390 °C led to 96 vol% phase-pure Ba2Ti9O20 from an initial mixture devoid of any dopant. Heat treatment at rates decreasing to 5 °C/min facilitated agglomeration of TiO2. This, in turn, increased the diffusion distance required for reaction of BaTi4O9 and TiO2 to form Ba2Ti9O20.


1994 ◽  
Vol 337 ◽  
Author(s):  
T.S. Kalkur ◽  
P.D. Wright

ABSTRACTTi/Pt and W/pt was used form contacts on hevily doped InAs and InGaAs emitter layers of heterojunction Bipolar transistors (HBTs) . The as deposited contacts were ohmic for Ti/Pt on InAs and W/Pt on InGaAs. The rapid thermal annealing was performed in the temperature range of 300-600 C. The contact characteristics of Ti/Pt and W/Pt were compared with Au/Cr contacts.


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