Self-Aligned, Metal-Masked Dry Etch Processing of III-V Electronic and Photonic Devices

1992 ◽  
Vol 260 ◽  
Author(s):  
S. J. Pearton ◽  
A. Katz ◽  
A. Feingold ◽  
F. Ren ◽  
T. R. Fullowan ◽  
...  
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Electron Cyclotron Resonance ◽  
Photonic Devices ◽  
Bipolar Transistors ◽  
Metal Contacts ◽  
Ecr Plasma ◽  
In Situ Fabrication ◽  
Device Processing ◽  
Integrated Processing ◽  
Dry Etch

ABSTRACTElectron Cyclotron Resonance (ECR) plasma etching of a variety of III-V devices, including heterojunction bipolar transistors (HBTs), and lasers will be reviewed. In many of these devices, the metal contacts also perform as self-aligned, dry etch masks, so that mask erosion must be addressed. Sidewall smoothness is also an issue for most etched mesa lasers, and conditions for achieving the requisite smoothness will be discussed. The use of stencil masks for pattern transfer of large (∼100μm) features during cluster-tool, single wafer integrated processing raises the possibility of a completely in-situ fabrication technology without the need for lithography. The dry etching of a variety of ohmic and Schottky metallizations and also of dielectrics deposited in a low pressure, rapid thermal CVD system lays the foundation for integrated III-V device processing.

Dry Etch Self-Aligned AlInAs/InGaAs Heterojunction Bipolar Transistors

1991 ◽  
Vol 240 ◽  
Author(s):  
T. R. Fullowan ◽  
S. J. Pearton ◽  
R. F. Kopf ◽  
F. Ren ◽  
Y. K. Chen ◽  
...  
Keyword(s):  
Plasma Etching ◽  
Heterojunction Bipolar Transistors ◽  
High Speed ◽  
Large Scale ◽  
Electron Cyclotron Resonance ◽  
Layer Structure ◽  
Digital Circuit ◽  
Bipolar Transistors ◽  
High Yield ◽  
Dry Etch

ABSTRACTA dry etch fabrication technology for high-speed AlInAs/InGaAs Heterojunction Bipolar Transistors (HBT's) utilizing low-damage Electron Cyclotron Resonance (ECR) CH4/H2/Ar plasma etching is detailed. The dry etch process uses triple self-alignment of the emitter and base metals and the base mesa, minimizing the base-collector capacitance (CBC). Devices with 2 × 4 μm2 emitters demonstrated current gains of 30–50 with ft and fmax values of ≥ 80 GHz and ≥100 GHz respectively. The structure employs a two-stage collector to achieve breakdown voltage (Vceo ) of 7V. The combination of processing and layer structure delivers truly scalable high yield AlInAs/InGaAs HBT's with both DC and RF characteristics suitable for large-scale, high speed digital circuit applications.

Tri-Layer Lift-off Metallization Process Using Low Temperature Deposited SiNx

1992 ◽  
Vol 282 ◽  
Author(s):  
J. R. Lothian ◽  
F. Ren ◽  
S. J. Pearton ◽  
U. K. Chakrabarti ◽  
C. R. Abernathy ◽  
...  
Keyword(s):  
Low Temperature ◽  
Heterojunction Bipolar Transistors ◽  
Electron Cyclotron Resonance ◽  
Bipolar Transistors ◽  
Base Layer ◽  
Lithographic Patterning ◽  
Final Stress ◽  
Lift Off ◽  
High Yields ◽  
Metallization Process

ABSTRACTA tri-level resist scheme using low temperature (<50°C) deposited SiNx ratfier than Ge for the transfer layer has been developed. This allows use of an optical stepper for lithographic patterning of the emitter-base junctions in GaAs/AlGaAs heterojunction bipolar transistors (HBTs) where a conventional lift-off process using a single level resist often leads to die presence of shorts between metallizations. The plasma-enhanced chemically vapor deposited (PECVD) SiNx shows a sligtly larger degree of Si-H bonding compared to nitride deposited at higher temperature (275°C), and is under compressive stress (-5 × 1010 dyne · cm−2) which is considerably relieved upor thermal cycling to 500°C (-1.5 × 1010 dyne · cm−2 after cool-down). This final stress is approximately a factor of two higher man conventional PECVD SiNx cycled in the same manner. The adhesion of the low temperature nitride to die underlying polydimediylglutarimide (PMGI) base layer in the tri-level resist is excellent, leading to high yields in the lift-off metallization process. These layers are etched in Electron Cyclotron Resonance (ECR) discharges of SF6 or O2, respectively, using low additional dc bias (≤-100V) on the sample. Subsequent deposition of the HBT base metallization (Ti/Ag/Au) and lift-off of the tri-level resist produces contacts with excellent edge definition and an absence of shorts between metallization.

Comparison of dry etch damage in GaAs/AlGaAs heterojunction bipolar transistors exposed to ECR and ICP Ar plasmas

1998 ◽  
Vol 42 (5) ◽  
pp. 733-742 ◽  
Author(s):  
J.W Lee ◽  
C.R Abernathy ◽  
S.J Pearton ◽  
F Ren ◽  
C Constantine ◽  
...  
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Bipolar Transistors ◽  
Dry Etch

Dry etch damage in inductively coupled plasma exposed GaAs/AlGaAs heterojunction bipolar transistors

1997 ◽  
Vol 70 (18) ◽  
pp. 2410-2412 ◽  
Author(s):  
F. Ren ◽  
J. W. Lee ◽  
C. R. Abernathy ◽  
S. J. Pearton ◽  
C. Constantine ◽  
...  
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Inductively Coupled Plasma ◽  
Bipolar Transistors ◽  
Inductively Coupled ◽  
Dry Etch

Integration of Si-MBE and Device Processing

1991 ◽  
Vol 220 ◽  
Author(s):  
D. J. Gravesteijn ◽  
G. F. A. Van De Walle ◽  
A. Pruijmboom ◽  
A. A. Van Gorkum
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Detrimental Effect ◽  
Defect Density ◽  
Bipolar Transistors ◽  
Current Gain ◽  
Gain Enhancement ◽  
Transient Diffusion ◽  
Device Processing ◽  
Background Doping ◽  
The Stability

ABSTRACTA review is given of the requirements on MBE-grown layers as far as processing is concerned. Aspects that are considered are: defect density, particulates, background doping and metallic contamination. The stability of the grown layers against thermal anneals is considered. It is shown that normal thermal diffusion in HBT structures is not important, other effects, like transient diffusion following ion implantation, have drastic effects on the grown profiles. As an example the processing of mesa-isolated heterojunction bipolar transistors is treated. It is shown that all-Si transistors can be grown with ideal Gummel plots. The Gummel plots of SiGe HBTs show small non-idealities. The current gain enhancement of the HBTs with respect to the all-Si transistors is shown to be as large as 200 times. Due to transient diffusion, parasitic barriers are formed, that have a detrimental effect on the AC and DC performance.

Surface precipitates on single crystal LiNbO3 after dry-etching by CHF3 plasma

1998 ◽  
Vol 13 (3) ◽  
pp. 527-529 ◽  
Author(s):  
Kaori Shima ◽  
Naoki Mitsugi ◽  
Hirotoshi Nagata
Keyword(s):  
Photoelectron Spectroscopy ◽  
Cyclotron Resonance ◽  
Auger Electron ◽  
Electron Cyclotron Resonance ◽  
Machining Process ◽  
Optical Modulators ◽  
X Ray ◽  
Ecr Plasma ◽  
Etched Surface ◽  
Dry Etch

The CHF3 electron cyclotron resonance (ECR) plasma etched LiNbO3 (LN) surface was analyzed chemically and crystallographically to investigate the dry-etch machining process for LN crystal, which was recently needed to obtain broader-band optical modulators. The etched surface was entirely covered with amorphous-like precipitates having ~70 nm diameter. These precipitates (or a part of them) were thought to be LiF from Auger electron and x-ray photoelectron spectroscopy. The results indicated that the LiF was formed and remained on the etched surface while the Nb was almost completely removed.

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