Dry Etch Self-Aligned AlInAs/InGaAs Heterojunction Bipolar Transistors

1991 ◽  
Vol 240 ◽  
Author(s):  
T. R. Fullowan ◽  
S. J. Pearton ◽  
R. F. Kopf ◽  
F. Ren ◽  
Y. K. Chen ◽  
...  

ABSTRACTA dry etch fabrication technology for high-speed AlInAs/InGaAs Heterojunction Bipolar Transistors (HBT's) utilizing low-damage Electron Cyclotron Resonance (ECR) CH4/H2/Ar plasma etching is detailed. The dry etch process uses triple self-alignment of the emitter and base metals and the base mesa, minimizing the base-collector capacitance (CBC). Devices with 2 × 4 μm2 emitters demonstrated current gains of 30–50 with ft and fmax values of ≥ 80 GHz and ≥100 GHz respectively. The structure employs a two-stage collector to achieve breakdown voltage (Vceo ) of 7V. The combination of processing and layer structure delivers truly scalable high yield AlInAs/InGaAs HBT's with both DC and RF characteristics suitable for large-scale, high speed digital circuit applications.

1992 ◽  
Vol 260 ◽  
Author(s):  
S. J. Pearton ◽  
A. Katz ◽  
A. Feingold ◽  
F. Ren ◽  
T. R. Fullowan ◽  
...  

ABSTRACTElectron Cyclotron Resonance (ECR) plasma etching of a variety of III-V devices, including heterojunction bipolar transistors (HBTs), and lasers will be reviewed. In many of these devices, the metal contacts also perform as self-aligned, dry etch masks, so that mask erosion must be addressed. Sidewall smoothness is also an issue for most etched mesa lasers, and conditions for achieving the requisite smoothness will be discussed. The use of stencil masks for pattern transfer of large (∼100μm) features during cluster-tool, single wafer integrated processing raises the possibility of a completely in-situ fabrication technology without the need for lithography. The dry etching of a variety of ohmic and Schottky metallizations and also of dielectrics deposited in a low pressure, rapid thermal CVD system lays the foundation for integrated III-V device processing.


Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.


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