Thermal Effects of Gasses in Rapid Thermal Processing

1991 ◽  
Vol 224 ◽  
Author(s):  
K. L. Knutson ◽  
S. A. Campbell ◽  
J. D. Leighton

AbstractA numerical model has been created for a Rapid Thermal Processing (RTP) system. Experiments have been done to show the validity of the model. The simulations done examine thermal uniformity and stresses incurred by RTP during steady state operation and during short time temperature ramps. It is shown that increasing the radiant intensity at the edge of the wafer reduces stress, compared to a uniform radiant field, in steadystate operation but increases stress during short time temperature ramps.

1991 ◽  
Vol 4 (1) ◽  
pp. 14-20 ◽  
Author(s):  
S.A. Campbell ◽  
K.-H. Ahn ◽  
K.L. Knutson ◽  
B.Y.H. Liu ◽  
J.D. Leighton

2008 ◽  
Vol 85 (11) ◽  
pp. 2282-2289 ◽  
Author(s):  
P.O. Logerais ◽  
D. Chapron ◽  
J. Garnier ◽  
A. Bouteville

2018 ◽  
Vol 8 (1) ◽  
Author(s):  
V. K. Judge ◽  
J. G. Speer ◽  
K. D. Clarke ◽  
K. O. Findley ◽  
A. J. Clarke

Abstract Quenching and Tempering (Q&T) has been utilized for decades to alter steel mechanical properties, particularly strength and toughness. While tempering typically increases toughness, a well-established phenomenon called tempered martensite embrittlement (TME) is known to occur during conventional Q&T. Here we show that short-time, rapid tempering can overcome TME to produce unprecedented property combinations that cannot be attained by conventional Q&T. Toughness is enhanced over 43% at a strength level of 1.7 GPa and strength is improved over 0.5 GPa at an impact toughness of 30 J. We also show that hardness and the tempering parameter (TP), developed by Holloman and Jaffe in 1945 and ubiquitous within the field, is insufficient for characterizing measured strengths, toughnesses, and microstructural conditions after rapid processing. Rapid tempering by energy-saving manufacturing processes like induction heating creates the opportunity for new Q&T steels for energy, defense, and transportation applications.


1986 ◽  
Vol 71 ◽  
Author(s):  
Tom Sedgwick

AbstractRapid Thermal Processing (RTP) can minimize processing time and therefore minimize dopant motion during annealing of ion implanted junctions. In spite of the advantage of short time annealing using RTP, the formation of shallow B junctions is thwarted by channeling, transient enhanced diffusion and concentration enhanced diffusion effects all of which lead to deeper B profiles. Channeling and transient enhanced diffusion can be avoided by preamorphizing the silicon before the B implant. However, defects at the original amorphous/crystal boundary persist after annealing. Very low energy B implantation can lead to very shallow dopant profiles and in spite of channeling effects, offers an attractive potential shallow junction technology. In all of the shallow junction formation techniques RTP is required to achieve both high activation of the implanted species and minimal diffusion of the implanted dopant.


1993 ◽  
Vol 303 ◽  
Author(s):  
Peter Y. Wong ◽  
Christopher K. Hess ◽  
Ioannis N. Miaoulis

ABSTRACTThe individual film thicknesses of multilayered structures processed by rapid thermal processing are of the same order as the wavelengths of the incident radiation. This induces optical interference effects which are responsible for the strong dependency of surface reflectivity, emissivity, and temperature distributions on the geometry of the layering structures, presence of patterns, and thickness of the films. A two-dimensional, finitedifference numerical model has been developed to investigate this microscale radiation phenomena and identify the critical processing parameters which affect rapid thermal processing of multilayer thin films. The uniformity of temperature distributions throughout the wafer during rapid thermal processing is directly affected by incident heater configurations, ramping conditions, wafer-edge effects, and thin-film layering structure. Results from the numerical model for various film structures are presented for chemical vapor deposition of polycrystalline silicon over oxide films on substrate. A novel technique using an edge-enhanced wafer which has a different film structure near its edge is presented as a control over the transient temperature distribution.


1987 ◽  
Vol 92 ◽  
Author(s):  
U. Neta ◽  
V. Richter ◽  
R. Kalish

ABSTRACTA new Rapid Thermal Processing technique based on heating by irradiation from CO2 laser is presented. It is particularly suitable for thermal treatment of low melting temperature materials such as annealing implantation induced damage in compound semiconductors.Short time heating of the sample is achieved by its contact with a quartz plate heated by photons from a CW CO2 laser. The quartz serves both as an absorbing medium for the radiation and as a proximity cap. Steady state temperature can be obtained by the simultaneous heating of the sample by the laser and its cooling by a jet of N2 gas.The present technique, when applied to ion implanted InSb (TA<450°C, t=10 seconds), leads to removal of the implantation damage which is comparable to that obtained by furnace or flash lamp (Heatpulse™)annealing.


1985 ◽  
Vol 52 ◽  
Author(s):  
Michael L. Reed ◽  
James D. Plummer

ABSTRACTRapid thermal processing is a promising tool for studying the kinetics of interface state annealing and other process phenomena on short time scales. We have studied the decay of interface states with a variety of ambients, temperatures, and oxide thicknesses. Annealing kinetics appear to be controlled by a surface reaction process, and not hydrogen diffusion through the oxide. The annealing behavior depends strongly on temperature but less so on other process parameters. Our experimental methodology for temporal process modeling is discussed.


1991 ◽  
Vol 224 ◽  
Author(s):  
T. Y. Hsieh ◽  
K. H. Jung ◽  
D. L. Kwong ◽  
S. Lin ◽  
H. L. Marcus

AbstractA short time high temperature H2 pre-bake resulted in an undulating SIMOX surface, which planarized after epitaxial growth by rapid thermal processing chemical vapor deposition (RTPCVD). However, a short time, high temperature N2 pre-bake resulted in severe surface pitting. From dilute Schimmel etch results, no significant changes in the defect densities of the Si layers occurred after RTPCVD. Auger depth profiles of the SOI substrate prior to epitaxial growth show an oxygen peak in the SIMOX Si layer. However, the peak flattens out after epitaxial growth. Oxygen was not observed in the epitaxial film, even though oxygen was still observed in the SIMOX top Si layer.The use of GexSi1−x epitaxial layers to reduce threading dislocation densities was examined. A 1000°C Si buffer layer was first grown for 30s, followed by a GexSi1−x layer, and topped off by a 1000°C Si layer for 120s. The GexSi1−x layers were grown at temperatures varying from 850°C to 1000°C for 30s to 240s. The defect density was significantly reduced when the 900°C and 850°C GexSi1−x layers were used, although an increase in stacking fault densities (still small compared to threading dislocation densities) accompanied the lower deposition temperatures. The 1000°C GexSi1−x layer and a control sample in which pure Si was grown showed no significant decrease in defect densities.


2006 ◽  
Vol 527-529 ◽  
pp. 1309-1312
Author(s):  
Ryouji Kosugi ◽  
Kenji Suzuki ◽  
Kazuto Takao ◽  
Yusuke Hayashi ◽  
Tsutomu Yatsuo ◽  
...  

A passivation annealing in nitric oxide (NO) ambient significantly reduces the interfacial defects of the SiO2/4H-SiC interface and improves the inversion MOS channel mobility. Effects of the nitridation in NO ambient become more pronounced at high temperatures in general. However, the maximum process temperature in a standard hot-wall oxidation furnace is restricted around 1200oC due to the softening point of quartz. Meanwhile, by use of a cold-wall oxidation furnace, high temperature and short time thermal processes become possible. In this study, we have developed an extremely high temperature (>1400oC) rapid thermal processing for the gate oxidation in the 4H-SiC DIMOSFET fabrication process. The peak MOS channel mobility of lateral MOSFETs on the DIMOSFET chip shows as high as 19cm2/Vs. The specific on-resistance of the device was 12.5mcm2 and the blocking voltage was 950V with gate shorted to the source.


Crystals ◽  
2020 ◽  
Vol 10 (5) ◽  
pp. 394 ◽  
Author(s):  
Erik Temmel ◽  
Jonathan Gänsch ◽  
Andreas Seidel-Morgenstern ◽  
Heike Lorenz

A recently developed continuous enantioseparation process utilizing two coupled fluidized bed crystallizers is systematically investigated to identify essential correlations between different operation parameters and the corresponding process performance on the example of asparagine monohydrate. Based on liquid phase composition and product crystal size distribution data, it is proven that steady state operation is achieved reproducibly in a relatively short time. The process outputs at steady state are compared for different feed flow rates, supersaturations, and crystallization temperatures. It is shown that purities >97% are achieved with productivities up to 40 g/L/h. The size distribution, which depends almost exclusively on the liquid flow rate, can be easily adjusted between 260 and 330 µm (mean size) with an almost constant standard deviation of ±55 µm.


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