High Density Metal Oxide (ZnO) Nanopatterned Platforms for Electronic Applications

2013 ◽  
Vol 1498 ◽  
pp. 255-261
Author(s):  
Vignesh Suresh ◽  
Meiyu Stella Huang ◽  
Madapusi.P. Srinivasan ◽  
Sivashankar Krishnamoorthy

ABSTRACTFabrication methodologies with high precision and tenability for nanostructures of metal and metal oxides are widely explored for engineering devices such as solar cells, sensors, non-volatile memories (NVM) etc. In this direction, metal and metal oxide nanopatterned arrays are the state-of-the-art platforms upon which the device structures are built where the tunable orderly arrangement of the nanostructures enhances the device performance. We describe here a coalition of fabrication protocols that employ block copolymer self-assembly and nanoimprint lithography (NIL) to obtain metal oxide nanopatterns with sub-100 nm spatial resolution. The protocols are easily scalable down to sub-50 nm and below.Nanopatterned arrays of ZnO created by using NIL assisted templates through area selective atomic layer deposition (ALD) and radio frequency (RF) sputtering find application in NVM and photovoltaics. We have employed NIL that produced nanoporous polymer templates using Si molds derived from block copolymer lithography (BCL) for pattern transfer into ZnO. The resulting ZnO nanoarrays were highly dense (8.6 x 109 nanofeatures per cm2) exhibiting periodic feature to feature spacing and width that replicated the geometric attributes of the template. Such nanopatterns find application in NVM, where a change in the density and periodicity of the arrays influences the charge storage characteristics. The above assembly and patterning protocols were employed to fabricate metal-oxide-semiconductor (MOS) capacitor devices for investigating application in NVM. Patterned ZnO nanoarrays were used as charge storage centres for the MOS capacitor devices. Preliminary results upon investigating the flash memory performance showed good flat-band voltage hysteresis window at a relatively low operating voltage due to high charge trap density.

2012 ◽  
Vol 101 (21) ◽  
pp. 212108 ◽  
Author(s):  
Souvik Kundu ◽  
Nripendra N. Halder ◽  
Pranab Biswas ◽  
D. Biswas ◽  
P. Banerji ◽  
...  

2001 ◽  
Vol 686 ◽  
Author(s):  
Puspashree Mishra ◽  
Shinji Nozaki ◽  
Ryuta Sakura ◽  
Hiroshi Morisaki ◽  
Hiroshi Ono ◽  
...  

AbstractCapacitance-Voltage (C-V) hysteresis was observed in the Metal-Oxide-Semiconductor (MOS) capacitor with silicon nanocrystals. The MOS capacitor was fabricated by thermal oxidation of Si nanocrystals, which were deposited on an ultra-thin thermal oxide grown previously on a p-type Si substrate. The Si nanocrystals were deposited by the gas evaporation technique with a supersonic jet nozzle. The size uniformity and the crystallinity of the Si nanocrystals are found to be better than those fabricated by the conventional gas evaporation technique. The C-V hysteresis in the MOS capacitor is attributed to electron charging and discharging of the nanocrystals by direct tunneling though the ultra-thin oxide between the nanocrystals and the substrate. The flat-band voltage shift observed during the C-V measurement depends on the size and density of the nanocrystals and also on the magnitude of the positive gate bias for charging. The retention characteristic is also discussed.


2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
J. H. Yum ◽  
J. Oh ◽  
Todd. W. Hudnall ◽  
C. W. Bielawski ◽  
G. Bersuker ◽  
...  

In a previous study, we have demonstrated that beryllium oxide (BeO) film grown by atomic layer deposition (ALD) on Si and III-V MOS devices has excellent electrical and physical characteristics. In this paper, we compare the electrical characteristics of inserting an ultrathin interfacial barrier layer such as SiO2, Al2O3, or BeO between the HfO2gate dielectric and Si substrate in metal oxide semiconductor capacitors (MOSCAPs) and n-channel inversion type metal oxide semiconductor field effect transistors (MOSFETs). Si MOSCAPs and MOSFETs with a BeO/HfO2gate stack exhibited high performance and reliability characteristics, including a 34% improvement in drive current, slightly better reduction in subthreshold swing, 42% increase in effective electron mobility at an electric field of 1 MV/cm, slightly low equivalent oxide thickness, less stress-induced flat-band voltage shift, less stress induced leakage current, and less interface charge.


Nanomaterials ◽  
2018 ◽  
Vol 8 (10) ◽  
pp. 799 ◽  
Author(s):  
Jer Wang ◽  
Chyuan Kao ◽  
Chien Wu ◽  
Chun Lin ◽  
Chih Lin

High-k material charge trapping nano-layers in flash memory applications have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants. In addition, Ti-doped high-k materials can improve memory device performance, such as leakage current reduction, k-value enhancement, and breakdown voltage increase. In this study, the structural and electrical properties of different annealing temperatures on the Nb2O5 and Ti-doped Nb2O5(TiNb2O7) materials used as charge-trapping nano-layers in metal-oxide-high k-oxide-semiconductor (MOHOS)-type memory were investigated using X-ray diffraction (XRD) and atomic force microscopy (AFM). Analysis of the C-V hysteresis curve shows that the flat-band shift (∆VFB) window of the TiNb2O7 charge-trapping nano-layer in a memory device can reach as high as 6.06 V. The larger memory window of the TiNb2O7 nano-layer is because of a better electrical and structural performance, compared to the Nb2O5 nano-layer.


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