scholarly journals Nb2O5 and Ti-Doped Nb2O5 Charge Trapping Nano-Layers Applied in Flash Memory

Nanomaterials ◽  
2018 ◽  
Vol 8 (10) ◽  
pp. 799 ◽  
Author(s):  
Jer Wang ◽  
Chyuan Kao ◽  
Chien Wu ◽  
Chun Lin ◽  
Chih Lin
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Dielectric Constants ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Hysteresis Curve ◽  
Band Shift ◽  
K Value ◽  
High K

High-k material charge trapping nano-layers in flash memory applications have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants. In addition, Ti-doped high-k materials can improve memory device performance, such as leakage current reduction, k-value enhancement, and breakdown voltage increase. In this study, the structural and electrical properties of different annealing temperatures on the Nb2O5 and Ti-doped Nb2O5(TiNb2O7) materials used as charge-trapping nano-layers in metal-oxide-high k-oxide-semiconductor (MOHOS)-type memory were investigated using X-ray diffraction (XRD) and atomic force microscopy (AFM). Analysis of the C-V hysteresis curve shows that the flat-band shift (∆VFB) window of the TiNb2O7 charge-trapping nano-layer in a memory device can reach as high as 6.06 V. The larger memory window of the TiNb2O7 nano-layer is because of a better electrical and structural performance, compared to the Nb2O5 nano-layer.

Electrical Characterization of High-k Dielectrics by Means of Flat-Band Voltage Transient Recording

2007 ◽  
Vol 996 ◽  
Author(s):  
Salvador Duenas ◽  
Helena Castán ◽  
Héctor García ◽  
Luis Bailón ◽  
Kaupo Kukli ◽  
...  
Keyword(s):  
Electric Fields ◽  
Electrical Characterization ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Localized States ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Flat Band Voltage ◽  
High K ◽  
Mos Structures

AbstractWe have carried out a comparison between flat-band transients displayed in metal-oxide-semiconductor (MOS) structures fabricated on several atomic layer deposited (ALD) high-k dielectric films: HfO2, ZrO2, Al2O3, Ta2O5, TiO2, and Gd2O3. The gate voltage as a function of time is recorded while keeping constant the capacitance at the initial flat band condition (CFB). Since samples are in darkness, under no electric fields and no charge-injection conditions, transients must be due to charge trapping of localized states produced by electrons (holes) coming from the semiconductor by tunnelling. The process is assisted by phonons and it is therefore thermally activated. The temperature-transient amplitude relation follows an Arrhenius plot which provides the thermal activation energy of soft-optical phonons. Finally, we describe the dependencies of the flat-band voltage on the setup bias history (accumulation or inversion) and the hysteresis sign (clockwise or counter-clockwise) of the capacitance-voltage (C-V) characteristics of MOS structures.

Charge-Trapping-Type Flash Memory Device With Stacked High-$k$ Charge-Trapping Layer

2009 ◽  
Vol 30 (7) ◽  
pp. 775-777 ◽  
Author(s):  
Ping-Hung Tsai ◽  
Kuei-Shu Chang-Liao ◽  
Te-Chiang Liu ◽  
Tien-Ko Wang ◽  
Pei-Jer Tzeng ◽  
...  
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
High K

Crucial integration of high work-function metal gate and high-k blocking oxide on charge-trapping type flash memory device

2008 ◽  
Vol 93 (25) ◽  
pp. 252902 ◽  
Author(s):  
Ping-Hung Tsai ◽  
Kuei-Shu Chang-Liao ◽  
Dong-Wei Yang ◽  
Yuan-Bin Chung ◽  
Tien-Ko Wang ◽  
...  
Keyword(s):  
Work Function ◽  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Metal Gate ◽  
High Work Function ◽  
High K ◽  
High Work

Enhanced Programming and Erasing Speeds in P-Channel Charge-Trapping Flash Memory Device With SiGe Buried Channel

2012 ◽  
Vol 33 (9) ◽  
pp. 1264-1266 ◽  
Author(s):  
Li-Jung Liu ◽  
Kuei-Shu Chang-Liao ◽  
Yi-Chuen Jian ◽  
Jen-Wei Cheng ◽  
Tien-Ko Wang ◽  
...  
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Buried Channel

scholarly journals Chemical-Vapor-Deposited Graphene as Charge Storage Layer in Flash Memory Device

2016 ◽  
Vol 2016 ◽  
pp. 1-6 ◽  
Author(s):  
W. J. Liu ◽  
L. Chen ◽  
P. Zhou ◽  
Q. Q. Sun ◽  
H. L. Lu ◽  
...  
Keyword(s):  
Flash Memory ◽  
Room Temperature ◽  
Metal Layer ◽  
Chemical Vapor ◽  
Charge Trapping ◽  
Memory Device ◽  
Water Molecules ◽  
Oh Groups ◽  
Chemical Vapor Deposited ◽  
A Charge

We demonstrated a flash memory device with chemical-vapor-deposited graphene as a charge trapping layer. It was found that the average RMS roughness of block oxide on graphene storage layer can be significantly reduced from 5.9 nm to 0.5 nm by inserting a seed metal layer, which was verified by AFM measurements. The memory window is 5.6 V for a dual sweep of ±12 V at room temperature. Moreover, a reduced hysteresis at the low temperature was observed, indicative of water molecules or −OH groups between graphene and dielectric playing an important role in memory windows.

Enhanced Programming and Erasing Speeds of Charge-Trapping Flash Memory Device With Ge Channel

2015 ◽  
Vol 36 (12) ◽  
pp. 1314-1317 ◽  
Author(s):  
Zong-Hao Ye ◽  
Kuei-Shu Chang-Liao ◽  
Li-Jung Liu ◽  
Jen-Wei Cheng ◽  
Hsin-Kai Fang
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device

Impacts of Electrical Field in Tunneling Layer on Operation Characteristics of Poly-Ge Charge-Trapping Flash Memory Device

2020 ◽  
Vol 41 (12) ◽  
pp. 1766-1769
Author(s):  
Hsin-Kai Fang ◽  
Kuei-Shu Chang-Liao ◽  
Kuan-Chi Chou ◽  
Tzu-Cheng Chao ◽  
Jung-En Tsai ◽  
...  
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Electrical Field ◽  
Operation Characteristics
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