Circuit Responses to Radiation-Induced Upsets

MRS Bulletin ◽  
2003 ◽  
Vol 28 (2) ◽  
pp. 126-130 ◽  
Author(s):  
Kerry Bernstein
Keyword(s):  
High Speed ◽  
Random Access ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Oxide Semiconductor ◽  
Access Memory ◽  
Radiation Induced ◽  
Radiation Circuit ◽  
Successive Generations ◽  
Common Logic

AbstractHistorically, radiation-induced corruption of data in high-speed complementary metal oxide semiconductor designs has been limited to on-board static random-access memory in various memory caches. Successive generations of scaling, however, have resulted in capacitance reductions in key logic circuits, increasing their vulnerability to these “soft errors.” Charge delivered by radiation events now carries a substantial probability of inducing upsets, not only in bistable elements, but in logic evaluation circuits as well. This article introduces the reader to common logic-circuit topologies in high-speed microprocessors, radiation circuit response mechanisms that can compromise logic evaluation integrity, and existing techniques that mitigate this exposure.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals Recent Progress in the Voltage-Controlled Magnetic Anisotropy Effect and the Challenges Faced in Developing Voltage-Torque MRAM

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 327 ◽  
Author(s):  
Takayuki Nozaki ◽  
Tatsuya Yamamoto ◽  
Shinji Miwa ◽  
Masahito Tsujikawa ◽  
Masafumi Shirai ◽  
...  
Keyword(s):  
Magnetic Anisotropy ◽  
High Speed ◽  
Recent Progress ◽  
Semiconductor Industry ◽  
Random Access ◽  
Complementary Metal Oxide Semiconductor ◽  
Electrical Current ◽  
High Energy ◽  
Oxide Semiconductor ◽  
Dynamic Switching

The electron spin degree of freedom can provide the functionality of “nonvolatility” in electronic devices. For example, magnetoresistive random access memory (MRAM) is expected as an ideal nonvolatile working memory, with high speed response, high write endurance, and good compatibility with complementary metal-oxide-semiconductor (CMOS) technologies. However, a challenging technical issue is to reduce the operating power. With the present technology, an electrical current is required to control the direction and dynamics of the spin. This consumes high energy when compared with electric-field controlled devices, such as those that are used in the semiconductor industry. A novel approach to overcome this problem is to use the voltage-controlled magnetic anisotropy (VCMA) effect, which draws attention to the development of a new type of MRAM that is controlled by voltage (voltage-torque MRAM). This paper reviews recent progress in experimental demonstrations of the VCMA effect. First, we present an overview of the early experimental observations of the VCMA effect in all-solid state devices, and follow this with an introduction of the concept of the voltage-induced dynamic switching technique. Subsequently, we describe recent progress in understanding of physical origin of the VCMA effect. Finally, new materials research to realize a highly-efficient VCMA effect and the verification of reliable voltage-induced dynamic switching with a low write error rate are introduced, followed by a discussion of the technical challenges that will be encountered in the future development of voltage-torque MRAM.

Molecular Memories Based on a CMOS Platform

MRS Bulletin ◽  
2004 ◽  
Vol 29 (11) ◽  
pp. 838-842 ◽  
Author(s):  
Werner G. Kuhr ◽  
Antonio R. Gallo ◽  
Robert W. Manning ◽  
Craig W. Rhodine
Keyword(s):  
Low Power ◽  
State Of The Art ◽  
Random Access ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Access Memory ◽  
Memory Element ◽  
Storage Mechanism ◽  
Charge Storage Mechanism ◽  
Power Operation

AbstractHybrid complementary metal oxide semiconductor (CMOS)/molecular memory devices are based on a dynamic random-access memory (DRAM) architecture, are fast, have high density, and exhibit low power consumption. These devices use a well-characterized charge storage mechanism to store information based on the intrinsic properties of molecules attached to a CMOS platform. The molecules are designed in a rational way to have known electrical properties and can be incorporated into CMOS devices with only minor modification of existing fabrication methods. Each memory element contains a monolayer of molecules (typically 100,000–1,000,000) to store charge; this process yields a structure that has many times the charge density of a typical DRAM capacitor, obviating the necessity for a trench or stacked capacitor geometry. The magnitude of voltage required to remove each electron is quantized (typically a few hundred millivolts per state), making it much easier to put molecules in a known state and to detect that state with low-power operation. Existing devices have charge retention times that are >1000 times that of semiconductors, and nonvolatile strategies based on simple modifications of existing systems are possible. All of these devices are ultimately scalable to molecular dimensions and will enable the production of memory products as small as state-of-the-art lithography will allow.

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