scholarly journals Recent Progress in the Voltage-Controlled Magnetic Anisotropy Effect and the Challenges Faced in Developing Voltage-Torque MRAM

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 327 ◽  
Author(s):  
Takayuki Nozaki ◽  
Tatsuya Yamamoto ◽  
Shinji Miwa ◽  
Masahito Tsujikawa ◽  
Masafumi Shirai ◽  
...  
Keyword(s):  
Magnetic Anisotropy ◽  
High Speed ◽  
Recent Progress ◽  
Semiconductor Industry ◽  
Random Access ◽  
Complementary Metal Oxide Semiconductor ◽  
Electrical Current ◽  
High Energy ◽  
Oxide Semiconductor ◽  
Dynamic Switching

The electron spin degree of freedom can provide the functionality of “nonvolatility” in electronic devices. For example, magnetoresistive random access memory (MRAM) is expected as an ideal nonvolatile working memory, with high speed response, high write endurance, and good compatibility with complementary metal-oxide-semiconductor (CMOS) technologies. However, a challenging technical issue is to reduce the operating power. With the present technology, an electrical current is required to control the direction and dynamics of the spin. This consumes high energy when compared with electric-field controlled devices, such as those that are used in the semiconductor industry. A novel approach to overcome this problem is to use the voltage-controlled magnetic anisotropy (VCMA) effect, which draws attention to the development of a new type of MRAM that is controlled by voltage (voltage-torque MRAM). This paper reviews recent progress in experimental demonstrations of the VCMA effect. First, we present an overview of the early experimental observations of the VCMA effect in all-solid state devices, and follow this with an introduction of the concept of the voltage-induced dynamic switching technique. Subsequently, we describe recent progress in understanding of physical origin of the VCMA effect. Finally, new materials research to realize a highly-efficient VCMA effect and the verification of reliable voltage-induced dynamic switching with a low write error rate are introduced, followed by a discussion of the technical challenges that will be encountered in the future development of voltage-torque MRAM.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications

2019 ◽  
Vol 9 (3) ◽  
pp. 21 ◽  
Author(s):  
Satheesh Kumar S ◽  
Kumaravel S
Keyword(s):  
Low Power ◽  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
High Energy ◽  
Oxide Semiconductor ◽  
High Energy Particle ◽  
Single Event Upset ◽  
Single Event ◽  
Clock Gating

Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation. In this paper, a low-power and high-speed single event upset radiation hardened latch is proposed. The proposed latch can withstand single event upsets completely when the high energy particle hit on any one of its intermediate nodes. The proposed latch structure comprises of four CMOS feedback schemes and a Muller C-element with clock gating technique. For the sake of comparison, the proposed and the existing latches in the literature are implemented in 45nm CMOS technology. From the post layout simulation results, it may be noted that the proposed latch achieves 8% low power consumption, 95% less delay, and a 94% reduction in power-delay-product compared to the existing single event upset resilient and single event tolerant latches. Monte Carlo simulations show that the proposed latch is less sensitive to process, voltage, and temperature variations in comparison with the existing hardened latches in the literature.

Circuit Responses to Radiation-Induced Upsets

MRS Bulletin ◽  
2003 ◽  
Vol 28 (2) ◽  
pp. 126-130 ◽  
Author(s):  
Kerry Bernstein
Keyword(s):  
High Speed ◽  
Random Access ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Oxide Semiconductor ◽  
Access Memory ◽  
Radiation Induced ◽  
Radiation Circuit ◽  
Successive Generations ◽  
Common Logic

AbstractHistorically, radiation-induced corruption of data in high-speed complementary metal oxide semiconductor designs has been limited to on-board static random-access memory in various memory caches. Successive generations of scaling, however, have resulted in capacitance reductions in key logic circuits, increasing their vulnerability to these “soft errors.” Charge delivered by radiation events now carries a substantial probability of inducing upsets, not only in bistable elements, but in logic evaluation circuits as well. This article introduces the reader to common logic-circuit topologies in high-speed microprocessors, radiation circuit response mechanisms that can compromise logic evaluation integrity, and existing techniques that mitigate this exposure.

scholarly journals Ferroelectric HfO2-based materials for next-generation ferroelectric memories

2016 ◽  
Vol 06 (02) ◽  
pp. 1630003 ◽  
Author(s):  
Zhen Fan ◽  
Jingsheng Chen ◽  
John Wang
Keyword(s):  
Random Access ◽  
Complementary Metal Oxide Semiconductor ◽  
Ferroelectric Materials ◽  
Oxide Semiconductor ◽  
Next Generation ◽  
New Class ◽  
Generation Cost ◽  
Potential Applications ◽  
Cost Efficient ◽  
Ferroelectric Memories

Ferroelectric random access memory (FeRAM) based on conventional ferroelectric perovskites, such as Pb(Zr,Ti)O3 and SrBi2Ta2O9, has encountered bottlenecks on memory density and cost, because those conventional perovskites suffer from various issues mainly including poor complementary metal-oxide-semiconductor (CMOS)-compatibility and limited scalability. Next-generation cost-efficient, high-density FeRAM shall therefore rely on a material revolution. Since the discovery of ferroelectricity in Si:HfO2 thin films in 2011, HfO2-based materials have aroused widespread interest in the field of FeRAM, because they are CMOS-compatible and can exhibit robust ferroelectricity even when the film thickness is scaled down to below 10 nm. A review on this new class of ferroelectric materials is therefore of great interest. In this paper, the most appealing topics about ferroelectric HfO2-based materials including origins of ferroelectricity, advantageous material properties, and current and potential applications in FeRAM, are briefly reviewed.

scholarly journals Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 369 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Nikos Mastorakis
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Performance Comparison ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Design Metrics ◽  
Ripple Carry Adder ◽  
Speed Performance

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

scholarly journals Ultrathin perpendicular magnetic anisotropy CoFeB free layers for highly efficient, high speed writing in spin-transfer-torque magnetic random access memory

2019 ◽  
Vol 9 (1) ◽  
Author(s):  
Jodi M. Iwata-Harms ◽  
Guenole Jan ◽  
Santiago Serrano-Guisan ◽  
Luc Thomas ◽  
Huanlong Liu ◽  
...  
Keyword(s):  
Magnetic Anisotropy ◽  
High Speed ◽  
Random Access ◽  
Perpendicular Magnetic Anisotropy ◽  
Spin Transfer Torque ◽  
Tunnel Barrier ◽  
Magnetic Memory ◽  
Material System ◽  
Highly Efficient ◽  
Memory Applications

AbstractPerpendicular magnetic anisotropy (PMA) ferromagnetic CoFeB with dual MgO interfaces is an attractive material system for realizing magnetic memory applications that require highly efficient, high speed current-induced magnetic switching. Using this structure, a sub-nanometer CoFeB layer has the potential to simultaneously exhibit efficient, high speed switching in accordance with the conservation of spin angular momentum, and high thermal stability owing to the enhanced interfacial PMA that arises from the two CoFeB-MgO interfaces. However, the difficulty in attaining PMA in ultrathin CoFeB layers has imposed the use of thicker CoFeB layers which are incompatible with high speed requirements. In this work, we succeeded in depositing a functional CoFeB layer as thin as five monolayers between two MgO interfaces using magnetron sputtering. Remarkably, the insertion of Mg within the CoFeB gave rise to an ultrathin CoFeB layer with large anisotropy, high saturation magnetization, and good annealing stability to temperatures upwards of 400 °C. When combined with a low resistance-area product MgO tunnel barrier, ultrathin CoFeB magnetic tunnel junctions (MTJs) demonstrate switching voltages below 500 mV at speeds as fast as 1 ns in 30 nm devices, thus opening a new realm of high speed and highly efficient nonvolatile memory applications.

scholarly journals Effects of Process Variations in a HCMOS IC using a Monte Carlo SPICE Simulation

2017 ◽  
pp. 11-16
Author(s):  
Widianto Widianto ◽  
Lailis Syafaah ◽  
Nurhadi Nurhadi
Keyword(s):  
Monte Carlo ◽  
Integrated Circuit ◽  
High Speed ◽  
Evaluation Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Process Variations ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Spice Simulation ◽  
Simulation Results

In this paper, effects of process variations in a HCMOS (High-Speed Complementary Metal Oxide Semiconductor) IC (Integrated Circuit) are examined using a Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. The variations of the IC are L and VTO variations. An evaluation method is used to evaluate the effects of the variations by modeling it using a normal (Gaussian) distribution. The simulation results show that the IC may be detected as a defective IC caused by the variations based on large supply currents flow to it. 

The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface

MRS Bulletin ◽  
1996 ◽  
Vol 21 (4) ◽  
pp. 38-44 ◽  
Author(s):  
F.K. LeGoues
Keyword(s):  
Metal Oxide ◽  
High Speed ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Strained Si

Recently much interest has been devoted to Si-based heteroepitaxy, and in particular, to the SiGe/Si system. This is mostly for economical reasons: Si-based technology is much more advanced, is widely available, and is cheaper than GaAs-based technology. SiGe opens the door to the exciting (and lucrative) area of Si-based high-performance devices, although optical applications are still limited to GaAs-based technology. Strained SiGe layers form the base of heterojunction bipolar transistors (HBTs), which are currently used in commercial high-speed analogue applications. They promise to be low-cost compared to their GaAs counterparts and give comparable performance in the 2-20-GHz regime. More recently we have started to investigate the use of relaxed SiGe layers, which opens the door to a wider range of application and to the use of SiGe in complementary metal oxide semiconductor (CMOS) devices, which comprise strained Si and SiGe layers. Some recent successes include record-breaking low-temperature electron mobility in modulation-doped layers where the mobility was found to be up to 50 times better than standard Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Even more recently, SiGe-basedp-type MOSFETS were built with oscillation frequency of up to 50 GHz, which is a new record, in anyp-type material for the same design rule.

Simulations and Modeling of TFET for Low Power Design

2016 ◽  
pp. 640-667 ◽  
Author(s):  
Sunil Kumar ◽  
Balwinder Raj
Keyword(s):  
Low Power ◽  
Semiconductor Industry ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Manufacturing Cost ◽  
Technology Advancement ◽  
Channel Effects ◽  
Tunnel Fets

In Complementary Metal-Oxide-Semiconductor (CMOS) technology, scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past four decades. However, as the technology advancement on nanometer scale regime for the purpose of building ultra-high density integrated electronic computers and extending performance, CMOS devices are facing fundamental problems such as increased leakage currents, large process parameter variations, short channel effects, increase in manufacturing cost, etc. The new technology must be energy efficient, dense, and enable more device function per unit area and time. There are many novel nanoscale semiconductor devices, this book chapter introduces and summarizes progress in the development of the Tunnel Field-Effect Transistors (TFETs) for low power design. Tunnel FETs are interesting devices for ultra-low power applications due to their steep sub-threshold swing (SS) and very low OFF-current. Tunnel FETs avoid the limit 60mv/decade by using quantum-mechanical Band-to-Band Tunneling (BTBT).

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