Self-aligned Copper Oxide Passivation Layer – A Study on the Reliability Effect

MRS Advances ◽  
2020 ◽  
Vol 5 (54-55) ◽  
pp. 2827-2836
Author(s):  
Jia Quan Su ◽  
Yue Kuo
Keyword(s):  
Copper Oxide ◽  
Void Formation ◽  
Copper Film ◽  
Surface Oxidation ◽  
Passivation Layer ◽  
Plasma Oxidation ◽  
Flux Divergence ◽  
Failure Times ◽  
Copper Line ◽  
Wide Line

AbstractThe reliability of the plasma etched copper lines with the self-aligned copper oxide passivation layer has been studied with the electromigration stress method. The oxide passivation layer was prepared by plasma oxidation, which covers the entire exposed copper line to prevent the surface oxidation under the ambient condition. The void formation and growth process reflect the line broken mechanism. Voids formed from grain boundary depletion and grain thinning were monitored by optical microscopes. The line failure times with respect to line width and current density were measured. The addition of the oxide passivation layer shortened the lifetime due to the poor heat transfer and copper diffusion, which accelerated the formation and growth of the voids. The narrow line has a longer lifetime than the wide line because of the fewer grain boundaries for flux divergence to form voids. The copper oxide passivation layer was formed self-aligned to the copper line. It also gettered copper atoms diffused from the bulk copper film.

Macroscale synthesis of CuO nanowires on FTO plane substrate

2019 ◽  
Vol 33 (11) ◽  
pp. 1950138 ◽  
Author(s):  
Yota Mabuchi ◽  
Rashid Norhana Mohamed ◽  
Xuyang Li ◽  
Jianbo Liang ◽  
Naoki Kishi ◽  
...  
Keyword(s):  
Copper Oxide ◽  
Tin Oxide ◽  
Copper Film ◽  
Entire Region ◽  
Cuo Nanowires

This study aims to fabricate copper oxide (CuO) nanowires by annealing a copper film formed on a charged film of fluorine-doped tin oxide (FTO). However, from the viewpoint of stress and growth of nanowires, it is difficult to mass-produce CuO nanowires on the entire region of the macro area on the plane substrate. In the proposed study, this was made possible by modifying the substrate’s structure.

scholarly journals Fabrication of temperature sensor based on copper oxide nanowires grown on titanium coated glass substrate

2018 ◽  
Vol 36 (3) ◽  
pp. 460-468 ◽  
Author(s):  
Ali A. Aljubouri ◽  
Abdulqader D. Faisal ◽  
Wafaa K. Khalef
Keyword(s):  
Copper Oxide ◽  
Temperature Sensor ◽  
Glass Substrate ◽  
Physical Vapor Deposition ◽  
Copper Film ◽  
High Sensitivity ◽  
Infrared Thermal Imaging ◽  
Oxide Nanowires ◽  
Vapor Deposition Technique ◽  
Physical Vapor Deposition Technique

AbstractSingle phase, adherent films of copper oxide nanowires (CuO NWs) were successfully grown on a glass substrate. Titanium nanofilm was pre-coated on the glass substrate to assist the growth of a layer adherent to the substrate. The copper film of 1.5 μm thickness was deposited via physical vapor deposition technique followed by thermal oxidation in air at various temperatures for 4 h. The product was characterized by X-ray diffraction (XRD), scanning electron microscopy (SEM), ultraviolet-visible (UV-Vis) and Fourier transformation infrared (FT-IR) spectroscopy to find the crystal structure, morphology, phases, and optical properties of the deposited films. The CuO NWs film with 60% transmittance at wavelengths greater than 800 nm was obtained. It can be used as an infrared thermal imaging filter and in optoelectronic devices. The fabricated temperature sensor exhibited high sensitivity in the temperature range of 20 °C to 180 °C.

Understanding the Cu Void Formation by TEM Failure Analysis

2014 ◽  
Author(s):  
Binghai Liu ◽  
Jie Zhu ◽  
Changqing Chen ◽  
Eddie Er ◽  
Siping Zhao ◽  
...  
Keyword(s):  
Electron Diffraction ◽  
Failure Analysis ◽  
Seed Layer ◽  
Void Formation ◽  
Surface Oxidation ◽  
Alkaline Condition ◽  
Electron Diffraction Analysis ◽  
Root Cause ◽  
Cu Cmp

Abstract In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.

Analysis of Geometrical and Microstructural Effects on Void Formation in Metallization: Observation and Modelling

1996 ◽  
Vol 428 ◽  
Author(s):  
W. C. Shih ◽  
A. Ghiti ◽  
K. S. Low ◽  
A. L. Greer ◽  
A. G. O'Neill ◽  
...  
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Void Formation ◽  
Grain Structure ◽  
Flux Divergence ◽  
Damage Development ◽  
Temperature Variations ◽  
Atomic Flux ◽  
Grain Structures ◽  
Microstructural Effects

AbstractThis paper reports the analysis of geometrical and microstructural effects on void formation in interconnects. Ion-beam machining is used to define segments for study at the cathode end of test lines. Scanning electron microscopy is used to observe damage development, focused ion beam microscopy to observe the corresponding grain structure. Finite-element calculations of self-consistent current density and temperature distributions in the conductor are used to predict damage locations both for a continuum material and for simulated grain structures. Cross-section changes in the line give temperature variations leading to divergences in atomic flux. Regions of high flux divergence are favoured for electromigration damage, but the precise sites of damage are determined by the grain structure, as shown both in the experiment and in the modelling.

Study of Microhardness and Young's Modulus of Copper Thin Film by Tip-Grit AFM Scratch Technology in Various Environments

2014 ◽  
Vol 626 ◽  
pp. 529-540
Author(s):  
Chao Chang Arthur Chen ◽  
Chun Chieh Chao ◽  
Kuo Wei Huang ◽  
Wei En Fu
Keyword(s):  
Thin Film ◽  
Young’S Modulus ◽  
Young's Modulus ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Copper Film ◽  
Passivation Layer ◽  
Force Model ◽  
Copper Thin Film ◽  
Loop Control

This paper is devoted to investigate an estimation methodology of micro hardness and Young’s modulus of reacted passivation layer of deposited copper thin film in dry and wet environment based a tip-grit atomic force microscope (TGAFM) scratch on copper thin film of silicon wafer. The TGAFM is a modification or attachment of a nanoor micron grit on the tip apex or cantilever beam of a closed-loop control AFM instrument. In this study, a diameter 800 nm SiO2 grit glued on the apex of the tip of AFM is used for experiment. Tip force model has been developed based on Hertzian model and Tresca criterion for stress-strain relationship from the geometries of scratch groove, depth and width to evaluate about microhardness and Young's modulus of copper thin film in regular air and DI-water. Experimental results show that the microhardness (H) is 1.62GPa and the Young's modulus (E) is 160.52GPa of copper thin film in DI-water environment. These mechanical properties of copper thin film is larger than the H= 1.52GPa and E= 126.04GPa for dry environment. Results of this study can be further explored to the grit force reaction on the passivation layer of copper film of chemical mechanical planarization (CMP) process development for semiconductor industry.

scholarly journals Nanoscale-Precision Removal of Copper in Integrated Circuits Based on a Hybrid Process of Plasma Oxidation and Femtosecond Laser Ablation

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1188
Author(s):  
Shuai Wang ◽  
Yaoyu Wang ◽  
Shizhuo Zhang ◽  
Lingfeng Wang ◽  
Shuai Chen ◽  
...  
Keyword(s):  
Laser Ablation ◽  
Integrated Circuits ◽  
Femtosecond Laser ◽  
Copper Oxide ◽  
Ablation Threshold ◽  
Femtosecond Laser Ablation ◽  
Hybrid Process ◽  
Plasma Oxidation ◽  
Fs Laser ◽  
Application Potential

Copper (Cu) is the main interconnect conductor for integrated circuits (IC), and its processing quality is very important to device performance. Herein, a hybrid process of plasma oxidation and femtosecond laser (fs-laser) ablation was proposed for the nanoscale precision removal of Cu in integrated circuits. In this hybrid process, the surface layer of Cu was oxidized to the copper oxide by plasma oxidation, and then the fs-laser with a laser fluence lower than the Cu ablation threshold was used to remove the copper oxide without damaging the underlying Cu. Theoretically, the surface temperature evolutions of Cu and copper oxide under the femtosecond laser were studied by the two-temperature model, and it was revealed that the ablation threshold of copper oxide is much lower than that of Cu. The experimental results showed that the ablation threshold of copper oxide is lower than that of Cu, which is consistent with the theoretical analysis. Using the hybrid process, a surface roughness of 3 nm and a removal accuracy of 4 nm were obtained in the process of Cu film processing, which were better than those obtained by fs-laser ablation. This demonstrated that the hybrid process has good application potential in the field of copper micromachining.

Amorphous Cu2-δO as Passivation Layer for Ultra Long Stability of Copper Oxide Nanowires in Photoelectrochemical Environments

2018 ◽  
Vol 165 (7) ◽  
pp. H417-H424 ◽  
Author(s):  
Sriya Banerjee ◽  
Fei Wu ◽  
Yoon Myung ◽  
Shawn Chatman ◽  
Dariusz M. Niedzwiedzki ◽  
...  
Keyword(s):  
Copper Oxide ◽  
Passivation Layer ◽  
Oxide Nanowires

scholarly journals Million-Line Failure Distributions for Narrow Interconnects

1997 ◽  
Vol 505 ◽  
Author(s):  
M. C. Bartelt ◽  
J. J. Hoyt ◽  
N. C. Bartelt ◽  
J. J. Dike ◽  
W. G. Wolfer
Keyword(s):  
Failure Time ◽  
Void Formation ◽  
Stress Evolution ◽  
Computationally Efficient ◽  
Failure Times ◽  
Grain Sizes ◽  
Relaxation Of Stresses ◽  
Interconnect Reliability ◽  
Local Relaxation ◽  
Failure Time Distributions

ABSTRACTWe examine the distribution of failure times in a simple and computationally efficient, yet reasonably authentic, model of interconnect reliability that allows consideration of statistically significant samples. The model includes an approximate description of the distribution of grain sizes and texture in narrow interconnects, an effective treatment of stress evolution associated with mass transport along grain boundaries, and local relaxation of stresses due to void formation. Failure time distributions for populations of idealized structures are analyzed to aid in interpretation of model behavior.

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