scholarly journals Thin Film Characterization on Cu/SnAg Solder Interface for 3D Packaging Technologies

MRS Advances ◽  
2020 ◽  
Vol 5 (37-38) ◽  
pp. 1929-1935
Author(s):  
Kimberly Beers ◽  
Andrew E. Hollowell ◽  
G. Bahar Basim
Keyword(s):  
Flip Chip ◽  
Processing Parameters ◽  
Wafer Surface ◽  
Bump Height ◽  
Treatment Techniques ◽  
Solder Bumps ◽  
3D Packaging ◽  
Snag Solder ◽  
Current Densities ◽  
Silicon Vias

AbstractCopper is a commonly used interconnect metal in microelectronic interconnects due to its exceptional electrical and thermal properties. Particularly in applications of the 2.5 and 3D integration, Cu is utilized in through-silicon-vias (TSVs) and flip chip interconnects between microelectronic chips for providing miniaturization, lower power and higher performance than current 2D packaging approaches. SnAg capped Cu pillars are a common high-density interconnect technology for flip chip bonding. For these interconnects, specific properties of the Cu surface, such as roughness and cleanliness, are an important factor in the process to ensure quality solder bumps. During electroplating, tight processing parameters must be met so that defects are avoided, and high bump uniformity is achieved. An understanding of the interactions at the solder and Cu pillar interface is needed, based on the electroplating parameters, to determine the best method for populating solder on the wafer surface. In this study, surface treatment techniques such as oxygen plasma cleaning were performed on the Cu surfaces and the SnAg plating chemistry for depositing the solder were evaluated through hull cell testing to qualitatively determine the range of current densities to investigate. It was observed that current density while plating played a large role in solder bump deposition morphology. At the higher current densities greater than 60 mA/cm2, bump height non-uniformity and dendritic growth are observed and at lower current densities, less than or equal to 60 mA/cm2, uniform, continuous bump height occurred.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Underfill Dispensing for 3D Die Stacking with Through Silicon Vias

2012 ◽  
Vol 2012 (1) ◽  
pp. 000548-000553 ◽  
Author(s):  
Fuliang Le ◽  
S. W. Ricky Lee ◽  
Jingshen Wu ◽  
Matthew M. F. Yuen
Keyword(s):  
Flip Chip ◽  
Through Silicon Vias ◽  
Flip Chips ◽  
Solder Bumps ◽  
Die Stacking ◽  
Chip Carrier ◽  
On Chip ◽  
Silicon Vias ◽  
3D Package

In this paper, a 3D stacked-die package is developed for the miniaturization and integration of electronic devices. The developed package has a stacked flip-chip-on-chip structure and eight flip chips are arranged in four vertical layers using four silicon chip carriers with through silicon vias (TSVs). In each layer, two flip chips are mounted on the silicon chip carrier with 100 um solder bumps, and multiple TSVs are fabricated in each silicon chip carrier for underfill dispensing purpose. The 3D module with four stacked layers is sequentially assembled by the standard surface mount reflow process and finally mounted to a substrate. In the underfill process, conventional I-pass underfill is used to fill up the gaps of the bottom two layers as it has relatively fast spreading speed. For the top two chip carriers, underfill is dispensed through TSVs to fill the gaps. Unlike the conventional underfill process, the encapsulant in this case would not flow in the gaps by the capillary effect unless the dispensed materials can obtain enough kinetic energy to overcome the surface tension at the end of TSVs, and thus, smooth sidewall, proper dispensing settings and optimized TSV pattern are needed. After underfill, detailed inspections are performed to verify the quality of encapsulation. The results show that the combined I-pass/TSV underfill process gives void-free encapsulation and perfect fillets for the stacked 3D package.

scholarly journals Cross interactions on interfacial compound formation of solder bumps and metallization layers during reflow

2004 ◽  
Vol 19 (12) ◽  
pp. 3654-3664 ◽  
Author(s):  
T.L. Shao ◽  
T.S. Chen ◽  
Y.M. Huang ◽  
Chih Chen
Keyword(s):  
Flip Chip ◽  
Driving Forces ◽  
The Other ◽  
Compound Formation ◽  
Bump Height ◽  
Performance Requirements ◽  
Substrate Side ◽  
Solder Bumps ◽  
Snpb Solder ◽  
Eutectic Snpb

While the dimension of solder bumps keeps shrinking to meet higher performance requirements, the formation of interfacial compounds may be affected more profoundly by the other side of metallization layer due to a smaller bump height. In this study, cross interactions on the formation of intermetallic compounds (IMCs) were investigated in eutectic SnPb, SnAg3.5, SnAg3.8Cu0.7, and SnSb5 solders jointed to Cu/Cr–Cu/Ti on the chip side and Au/Ni metallization on the substrate side. It is found that the Cu atoms on the chip side diffused to the substrate side to form (Cux,Ni1−x)6Sn5 or (Niy,Cu1−y)3Sn4 for the four solders during the reflow for joining flip chip packages. For the SnPb solder, Au atoms were observed on the chip side after the reflow, yet few Ni atoms were detected on the chip side. In addition, for SnAg3.5 and SnSn5 solders, the Ni atoms on the substrate side migrated to the chip side during the reflow to change binary Cu6Sn5 into ternary (Cux,Ni1−x)6Sn5 IMCs, in which the Ni weighed approximately 21%. Furthermore, it is intriguing that no Ni atoms were detected on the chip side of the SnAg3.8Cu0.7 joint. The possible driving forces responsible for the diffusion of Au, Ni, and Cu atoms are discussed in this paper.

High-speed SnAG Solder Electroplating Process and Developments on Cost Reduction

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000717-000753
Author(s):  
Bob Forman
Keyword(s):  
High Speed ◽  
Consumer Electronics ◽  
Wafer Level ◽  
Solder Bumps ◽  
New Process ◽  
Snag Solder ◽  
Single Use ◽  
Current Densities ◽  
Electroplating Process ◽  
Short Time

The use of wafer level packaged ICs with Lead (Pb) free Tin Silver (SnAg) solder bumps is prevalent in consumer electronics. One method of making these bumps is by electroplating. The current process requires the use of a complex and expensive, single use chemistry. These chemistries do provide smooth, void free bumps, but with a very high Cost of Ownership (COO). Up to now these chemistries were expensive to operate, mainly because they are used for a short time and then disposed. This paper will discuss a new process using chemistry that provides improved COO by incorporating higher plating rates with recycling of used chemistry. With this process it is possible to recover nearly 100% of the metals, acids and organic agents previously discharged as waste. The recovered chemistry is then processed and certified to be reused in the originating fab, resulting in virtually zero waste. In addition to closed loop recycling, the process also forms bumps at a higher rate, by plating at higher current densities, with no trade-off in bump performance.

Robust Underfill Selection Methodology for Flip Chip

2007 ◽  
Author(s):  
Nokibul Islam ◽  
Miguel Jimarez ◽  
Robert Darveaux ◽  
JoonYeob Lee ◽  
JaeYoung Na ◽  
...  
Keyword(s):  
Body Size ◽  
Flip Chip ◽  
Temperature Cycle ◽  
Adhesion Properties ◽  
Bump Height ◽  
Sequential Selection ◽  
Solder Bumps ◽  
Modeling Data ◽  
Free Solder ◽  
Selection Methodology

Underfill is one of the crucial materials in flip chip (FC) packages. The role of underfill is not only to protect the solder bumps but to minimize package warpage, and to protect the fragile low k dielectric at end of line (EOL), moisture resistance test (MRT), and temperature cycle B (TCB) conditions. As packages move towards green products, the complexity of selecting a good underfill increases. The interaction of high Pb or eutectic solder with the underfill is different than that of Pb free solder. Moreover Pb free solder behavior for FC bumps is just being explored in the literature. Besides Pb free solder, other parameters like die passivation, bump height and pitch, under bump metallurgy (UBM) metallization, and package substrate are also extremely important for underfill selection. As the design of the package continues to change smaller package, tighter bump pitch and thinner core and build up (BU) layers, all of these parameters are directly related to package reliability. Sometimes an underfill good for a smaller die, body size, taller bump height, and pitch doesn’t necessarily mean it will be appropriate for a bigger die with larger body, and tighter bumps. So there are lots of variables in the package that directly affect the reliability. A good underfill should have very good adhesion between underfill and die passivation at room temperature, and moderate adhesion at underfill Tg. Adhesion properties are solely depend on chemistry of the underfill. Therefore to determine a good underfill for a bigger die and body size, we need to have a sequential selection methodology. In this paper a sequential selection methodology is used to eliminate the unsuccessful underfill candidates and select the best one which comfortably satisfies the requirements for all different solder alloys, and a wider range of package geometries. Important selection criteria including underfill workability issues and modeling data are also discussed.

Measurement of electromigration activation energy in eutectic SnPb and SnAg flip-chip solder joints with Cu and Ni under-bump metallization

2010 ◽  
Vol 25 (9) ◽  
pp. 1847-1853 ◽  
Author(s):  
Hsiao-Yun Chen ◽  
Chih Chen
Keyword(s):  
Activation Energy ◽  
Flip Chip ◽  
Void Formation ◽  
Under Bump Metallization ◽  
Solder Bumps ◽  
Snpb Solder ◽  
Snag Solder ◽  
Temperature Coefficient Of Resistivity ◽  
Eutectic Snpb ◽  
Real Temperature

Electromigration activation energy is measured by a built-in sensor that detects the real temperature during current stressing. Activation energy can be accurately determined by calibrating the temperature using the temperature coefficient of resistivity of an Al trace. The activation energies for eutectic SnAg and SnPb solder bumps are measured on Cu under-bump metallization (UBM) as 1.06 and 0.87 eV, respectively. The activation energy mainly depends on the formation of Cu–Sn intermetallic compounds. On the other hand, the activation energy for eutectic SnAg solder bumps with Cu–Ni UBM is measured as 0.84 eV, which is mainly related to void formation in the solder.

SOLDERABLE ANISOTROPIC CONDUCTIVE ADHESIVES FOR 3D PACKAGE APPLICATIONS

2014 ◽  
Vol 2014 (1) ◽  
pp. 000165-000169
Author(s):  
Mary Liu ◽  
Wusheng Yin
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Low Cost ◽  
Organic Substrate ◽  
Advanced Materials ◽  
Assembly Process ◽  
Conductive Adhesives ◽  
Bump Height ◽  
3D Packaging ◽  
3D Package

3D packaging has recently become very attractive because it can provide more flexibility in device design and supply chain, reduce the gap between silicon die and organic substrate, help miniaturize devices and meet the demand of high speed, provide more memory, more function and low cost. With the advancement of 3D packaging, the bump height is now down from 80μ to 10μ. When the bump diameter is 20–40μ and height 10μ, the process and reliability are obvious issues. It is well known that underfill can enhance the reliability for regular flip chip, however underfill won't help assembly process. In order to resolve some difficulties that 3D packaging faces, YINCAE Advanced Materials, LLC has developed solderable anisotropic conductive adhesives for 3D package applications. In this paper we will discuss the assembly process and reliability in detail.

Tensile fracture behaviors of solid-state-annealed eutectic SnPb and lead-free solder flip chip bumps

2004 ◽  
Vol 19 (6) ◽  
pp. 1826-1834 ◽  
Author(s):  
Jin-Wook Jang ◽  
Ananda P. De Silva ◽  
Jong-Kai Lin ◽  
Darrel R. Frear
Keyword(s):  
Solid State ◽  
Fracture Behavior ◽  
Flip Chip ◽  
Interfacial Fracture ◽  
Bulk Solder ◽  
Tensile Fracture ◽  
Solder Bumps ◽  
Snag Solder ◽  
Free Solder ◽  
Eutectic Snpb

The tensile fracture behavior for solid-state-annealed eutectic SnPb and lead-free solder flip chip bumps was examined. The annealing temperatures were in the range of 125–170 °C for 500 h. Prior to solid state annealing, the eutectic Sn–37Pb (SnPb) and Sn–0.7Cu (SnCu) solders showed fracture through the bulk solder. Brittle interfacial fracture occurred in the Sn–3.5Ag (SnAg) solder. After solid-state annealing, the fracture behavior changed dramatically. For eutectic SnPb solder, the fracture modes gradually changed from cohesive solder failure to interfacial fracture with increasing annealing temperature. The fracture mode of the SnCu solder showed greater change than the SnPb and SnCu solders. After annealing at 125 °C, the SnAg solder had a ductile taffy pull fracture, but an increase in temperature resulted in brittle interfacial fracture again. The SnCu solder maintained the same ductile taffy pull mode up to170 °C annealing, independent of the under bump metallization (UBM) type. Microstructure analysis showed that the interfacial fracture of the SnPb and SnAg solder bumps was ascribed to Pb-rich layer formation and Ag embrittlement at the interface, respectively. The bulk solder fracture of SnAg annealed at 125 °C appeared to be a transient phenomenon due to the abrupt breakdown of the hard lamella structure. The eutectic SnCu solder bumps had no significant change in the interfacial structure, except for interfacial intermetallic growth.

3D Glass and Silicon Interposers with TPV vs. 3D ICs with TSV

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000757-000790 ◽  
Author(s):  
Rao Tummala
Keyword(s):  
Flip Chip ◽  
Lower Cost ◽  
Low Cost ◽  
Georgia Tech ◽  
Natural Evolution ◽  
3 Dimensional ◽  
3D Ics ◽  
The Status ◽  
3D Packaging ◽  
Silicon Vias

3D Packaging has been emerging as the dominant theme for more than a decade. It started as package on package stacking in the 1970s for memory devices. More recently, it moved to stacked, wire bonded chips as well as miniaturized package-on-package (POP). Stacking with flip chip soon followed. In all these cases, ICs are fabricated in wafer fabs and packaging of these ICs was subsequently performed independently. The next natural evolution to be expected is to eliminate external interconnections outside the ICs by means of through vias, now called TSVs. But this became revolutionary, complex and costly. It impacted wafer fabrication by virtue of having to co-process transistors, BEOL wiring and TSV interconnections, all in the wafer fab. This is referred to as 3D ICs with TSV. The benefits of 3D ICs are overwhelming. They include highest performance in smallest size by virtue of stacking many ultra-thin ICs and interconnecting them with through-silicon-vias. But such a technology is also complex and costly to manufacture. It presents many other problems that include thermal management, testability, and extendibility. Georgia Tech PRC proposes to demonstrate lower cost and simpler 3D Interposers with TPVs to address most of the above challenges. In this scenario, through-package-vias (TPV) are fabricated in the ultra-thin and low-cost silicon or glass interposers at the same I/O density or pitch as in TSVs in the logic ICs but without the need for TSVs in the logic ICs. Such a concept is 3-dimensional; allowing stacking of ICs on both sides of the interposer with the same I/O pitch as TSVs and yet minimizes the thermal, testability and extendibility problems. This paper presents the status, progress and remaining challenges of 3D Interposer concept at Georgia Tech involving more than 25 companies in a global consortium.

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