Robust Underfill Selection Methodology for Flip Chip

2007 ◽  
Author(s):  
Nokibul Islam ◽  
Miguel Jimarez ◽  
Robert Darveaux ◽  
JoonYeob Lee ◽  
JaeYoung Na ◽  
...  
Keyword(s):  
Body Size ◽  
Flip Chip ◽  
Temperature Cycle ◽  
Adhesion Properties ◽  
Bump Height ◽  
Sequential Selection ◽  
Solder Bumps ◽  
Modeling Data ◽  
Free Solder ◽  
Selection Methodology

Underfill is one of the crucial materials in flip chip (FC) packages. The role of underfill is not only to protect the solder bumps but to minimize package warpage, and to protect the fragile low k dielectric at end of line (EOL), moisture resistance test (MRT), and temperature cycle B (TCB) conditions. As packages move towards green products, the complexity of selecting a good underfill increases. The interaction of high Pb or eutectic solder with the underfill is different than that of Pb free solder. Moreover Pb free solder behavior for FC bumps is just being explored in the literature. Besides Pb free solder, other parameters like die passivation, bump height and pitch, under bump metallurgy (UBM) metallization, and package substrate are also extremely important for underfill selection. As the design of the package continues to change smaller package, tighter bump pitch and thinner core and build up (BU) layers, all of these parameters are directly related to package reliability. Sometimes an underfill good for a smaller die, body size, taller bump height, and pitch doesn’t necessarily mean it will be appropriate for a bigger die with larger body, and tighter bumps. So there are lots of variables in the package that directly affect the reliability. A good underfill should have very good adhesion between underfill and die passivation at room temperature, and moderate adhesion at underfill Tg. Adhesion properties are solely depend on chemistry of the underfill. Therefore to determine a good underfill for a bigger die and body size, we need to have a sequential selection methodology. In this paper a sequential selection methodology is used to eliminate the unsuccessful underfill candidates and select the best one which comfortably satisfies the requirements for all different solder alloys, and a wider range of package geometries. Important selection criteria including underfill workability issues and modeling data are also discussed.

Study on electromigration in flip chip lead-free solder connections with 40 μm or 30 μm diameter on thin film ceramic substrates

2015 ◽  
Vol 2015 (1) ◽  
pp. 000799-000805
Author(s):  
Marek Gorywoda ◽  
Rainer Dohle ◽  
Bernd Kandler ◽  
Bernd Burger
Keyword(s):  
Thin Film ◽  
High Stability ◽  
Flip Chip ◽  
Lead Free ◽  
Published Data ◽  
Organic Substrates ◽  
Lead Free Solder ◽  
Ceramic Substrates ◽  
Solder Bumps ◽  
Free Solder

Electromigration comprises one of the processes affecting the long-term reliability of electronic devices; it has therefore been the focus of many investigations in recent years. In regards to flip chip packaging technology, the majority of published data is concerned with electromigration in solder connections to metallized organic substrates. Hardly any information is available in the literature on electromigration in lead-free solder connections on thin film ceramic substrates. This work presents results of a study of electromigration in lead-free (SAC305) flip chip solder bumps with a nominal diameter of 40 μm or 30 μm with a pitch of 100 μm on silicon chips assembled onto thin film Al2O3 ceramic substrates. The under bump metallization (UBM) comprised of a 5 μm thick electroless nickel immersion gold (ENIG) layer directly deposited on the AlCu0.5 trace. The ceramic substrates were metallized using a thin film multilayer (NiCr-Au(1.5 μm)-Ni(2 μm) structure on the top of which wettable areas were produced with high precision by depositing flash Au (60 nm) of the required diameter (40 μm or 30 μm). All electromigration tests were performed at the temperature of 125 °C. Initially, one chip assembly with 40 μm and one with 30 μm solder bumps was loaded with the current density of 8 kA/cm2 for 1,000 h. The assemblies did not fail and an investigation with SEM revealed no significant changes to the microstructure of the bumps. Thereafter seven chip assemblies with 40 μm solder bumps and five assemblies with 30 μm bumps were subjected to electromigration tests of 14 kA/cm2 or 25 kA/cm2, respectively. Six of the 40 μm-assemblies failed after 7,000 h and none of the 30 μm-assemblies failed after 2,500 h of test duration so far. Investigation of failed samples performed with SEM and EDX showed asymmetric changes of microstructure in respect to current flow. Several intermetallic phases were found to form in the solder. The predominant damage of the interconnects was found to occur at the cathode contact to chip; the Ni-P layers there showed typical columnar Kirkendall voids caused by migration of Ni from the layers into the solder. Failure of the contacts apparently occurred at the interface between Ni-P and solder. In summary, the results of the study indicate a very high stability of lead-free solder connections on ceramic substrates against electromigration. This high stability is primarily due to a better heat dissipation and thus to a relatively low temperature increase of the ceramic packages caused by resistive heating during flow of electric current. In addition, the type of the metallization used in the study seems to be more resistant to electromigration than the standard PCB metallization as it does not contain a copper layer.

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

2015 ◽  
Vol 2015 (1) ◽  
pp. 000787-000792
Author(s):  
E. Misra ◽  
T. Wassick ◽  
I. Melville ◽  
K. Tunga ◽  
D. Questad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Lead Free ◽  
Solder Interconnects ◽  
Design Changes ◽  
Modeling Data ◽  
Free Solder ◽  
Low K

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

The Study on The Under Bump Metallurgy (Ubm) and 63SN-37PB Solder Bumps Interface for Flip Chip Interconnection

1998 ◽  
Vol 515 ◽  
Author(s):  
Se-Young Jang ◽  
Kyung-Wook Paik
Keyword(s):  
Shear Strength ◽  
Direct Contact ◽  
Flip Chip ◽  
Organic Substrates ◽  
Adhesion Properties ◽  
Ball Shear ◽  
Solder Bumps ◽  
Diffusion Barrier Layer ◽  
Solder Reflow ◽  
Ball Shear Strength

ABSTRACTIn the flip chip interconnection on organic substrates using eutectic Pb/Sn solder bumps, highly reliable Under Bump Metallurgy (UBM) is required to maintain adhesion and solder wettability. Various UBM systems such as l.tm Al/0.2 μm Ti/5 μm Cu, l μm A1/0.2 μm Ti/l μm Cu, 1 μm A1/0.2 μm Ni/1 μm Cu and 1 μm At/10.2μm Pd/l μm Cu, laid under eutectic Pb/Sn solder of low melting point, were investigated with regard to their interfacial reactions and adhesion properties. The effects of numbers of solder reflow and aging time on the growth of intermetallic compounds (IMC) and on the solder ball shear strength were investigated. Good ball shear strength was obtained with 1 μm AI/0.2μm Ti/5μm Cu and 1 μm Al/0.2 μm Ni/l μm Cu even after 4 solder reflows or 7 day aging at 150°C. In contrast, l μm Al/0.2 μm Ti/l μm Cu and l μm A1/0.21μm Pd/μm Cu shows poor ball shear strength. The decrease of the shear strength was mainly due to the direct contact between solder and nonwettable metal such as Ti and Al resulting in a delamination. Thin 1 μm Cu and 0.2 μm Pd diffusion barrier layer were completely consumed by Cu-Sn and Pd-Sn reaction.

scholarly journals Cross interactions on interfacial compound formation of solder bumps and metallization layers during reflow

2004 ◽  
Vol 19 (12) ◽  
pp. 3654-3664 ◽  
Author(s):  
T.L. Shao ◽  
T.S. Chen ◽  
Y.M. Huang ◽  
Chih Chen
Keyword(s):  
Flip Chip ◽  
Driving Forces ◽  
The Other ◽  
Compound Formation ◽  
Bump Height ◽  
Performance Requirements ◽  
Substrate Side ◽  
Solder Bumps ◽  
Snpb Solder ◽  
Eutectic Snpb

While the dimension of solder bumps keeps shrinking to meet higher performance requirements, the formation of interfacial compounds may be affected more profoundly by the other side of metallization layer due to a smaller bump height. In this study, cross interactions on the formation of intermetallic compounds (IMCs) were investigated in eutectic SnPb, SnAg3.5, SnAg3.8Cu0.7, and SnSb5 solders jointed to Cu/Cr–Cu/Ti on the chip side and Au/Ni metallization on the substrate side. It is found that the Cu atoms on the chip side diffused to the substrate side to form (Cux,Ni1−x)6Sn5 or (Niy,Cu1−y)3Sn4 for the four solders during the reflow for joining flip chip packages. For the SnPb solder, Au atoms were observed on the chip side after the reflow, yet few Ni atoms were detected on the chip side. In addition, for SnAg3.5 and SnSn5 solders, the Ni atoms on the substrate side migrated to the chip side during the reflow to change binary Cu6Sn5 into ternary (Cux,Ni1−x)6Sn5 IMCs, in which the Ni weighed approximately 21%. Furthermore, it is intriguing that no Ni atoms were detected on the chip side of the SnAg3.8Cu0.7 joint. The possible driving forces responsible for the diffusion of Au, Ni, and Cu atoms are discussed in this paper.

Experimental Study of Void Formation in Eutectic and Lead-Free Solder Bumps of Flip-Chip Assemblies

2005 ◽  
Vol 128 (3) ◽  
pp. 202-207 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Experimental Study ◽  
Heat Flux ◽  
Flip Chip ◽  
Void Formation ◽  
Lead Free ◽  
Void Volume ◽  
Lead Free Solder ◽  
Solder Bumps ◽  
Free Solder ◽  
High Lead

This paper reports the experimental findings of void formation in eutectic and lead-free solder joints of flip-chip assemblies. A previous theory indicated that the formation of voids is determined by the direction of heating. The experiments were designed to examine the size and location of voids in the solder samples subject to different heat flux directions. A lead-free solder (Sn-3.5Ag-0.75Cu) and a eutectic solder (63Sn37Pb) were employed in the experiments. Previous experiments [Wang, D., and Panton, R. L., 2005, “Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies,” ASME J. Electron. Packag., 127(2), pp. 120–126; 2005, “Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps,” ASME J. Electron. Packag., 127(4), pp. 440–445] employed a high lead solder. 288 solder bumps were processed for each solder. Both eutectic and lead-free solder have shown fewer voids and much smaller void volume than those for high-lead solder. Compared with lead-free solder, eutectic solder has a slightly lower void volume and a lower percentage of defective bumps. For both eutectic and lead-free solders, irrespective of the cooling direction, heating solder samples from the top shows fewer defective bumps and smaller void volume. No significant effect on void formation for either eutectic or lead-free solder was found via reversing the heat flux direction during cooling. Unlike high-lead solder, small voids in eutectic or lead-free solder comprised 35-88% of the total void volume. The final distribution of voids shows a moderate agreement with thermocapillary theory, indicating the significance of the temperature gradient on the formation of voids.

Design and Fabrication of MEMS Based Microphone Module by Using 3D Chip-on-Chip Package

2007 ◽  
Author(s):  
Jeffery C. C. Lo ◽  
S. W. Ricky Lee
Keyword(s):  
Flip Chip ◽  
Lead Free Solder ◽  
Process Flow ◽  
Wire Bonds ◽  
Solder Bumps ◽  
Preliminary Study ◽  
Mems Device ◽  
Free Solder ◽  
On Chip ◽  
Electrical Connections

Packaging of the MEMS based microphone is very important as the sensing diaphragm is very fragile. A suitable packaging method is required for the MEMS based microphone. In order to have a better understanding of packaging related issues of microphone, commercially available MEMS based microphone package is studied. Based on the preliminary study, a 3D Chip-on-Chip modulus is selected. The detail process flow of the mentioned package will be discussed in the following sections. Flip chip with lead free solder bumps are used in the proposed 3D Chip-on-Chip modulus. In contrast, wire bonds are used in the commercial MEMS based microphone for electrical connections while die attached is used to provide the mechanical support. The advantages of using flip chip over wire bond in both manufacturability and reliability aspects are discussed. Several MEMS based microphone packaging related issues are studied and evaluated. The detail fabrication and assembly process flow will be presented. A prototype package with MEMS device is fabricated. It can be shown that the proposed 3D Chip-on-Chip modulus is feasible for packaging MEMS based microphone.

Modelling the Performance of Lead-Free Solder Interconnects for Copper Bumped Flip-Chip Devices

2003 ◽  
Author(s):  
Hua Lu ◽  
Chris Bailey
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Conductive Adhesives ◽  
Solder Interconnects ◽  
Flip Chips ◽  
Solder Bumps ◽  
Solder Volume ◽  
Joint Properties ◽  
Free Solder

Traditionally, before flip chips can be assembled the dies have to be attached with solder bumps. This process involves the deposition of metal layers on the Al pads on the dies and this is called the under bump metallurgy (UBM). In an alternative process, however, Copper (Cu) columns can be used to replace solder bumps and the UBM process may be omitted altogether. After the bumping process, the bumped dies can be assembled on to the printed circuit board (PCB) by using either solder or conductive adhesives. In this work, the reliability issues of flip chips with Cu column bumped dies have been studied. The flip chip lifetime associated with the solder fatigue failure has been modeled for a range of geometric parameters. The relative importance of these parameters is given and solder volume has been identified as the most important design parameter for long-term reliability. Another important problem that has been studied in this work is the dissolution of protection metals on the pad and Cu column in the reflow process. For small solder joints the amount of Cu which dissolves into the molten solder after the protection layers have worn out may significantly affect solder joint properties.

Novel flip-chip bonding technology for W-band interconnections using alternate lead-free solder bumps

2002 ◽  
Vol 12 (10) ◽  
pp. 372-374 ◽  
Author(s):  
K. Onodera ◽  
T. Ishii ◽  
S. Aoyama ◽  
S. Sugitani ◽  
M. Tokumitsu
Keyword(s):  
Flip Chip ◽  
Lead Free ◽  
Lead Free Solder ◽  
Flip Chip Bonding ◽  
W Band ◽  
Solder Bumps ◽  
Bonding Technology ◽  
Free Solder

scholarly journals Thin Film Characterization on Cu/SnAg Solder Interface for 3D Packaging Technologies

MRS Advances ◽  
2020 ◽  
Vol 5 (37-38) ◽  
pp. 1929-1935
Author(s):  
Kimberly Beers ◽  
Andrew E. Hollowell ◽  
G. Bahar Basim
Keyword(s):  
Flip Chip ◽  
Processing Parameters ◽  
Wafer Surface ◽  
Bump Height ◽  
Treatment Techniques ◽  
Solder Bumps ◽  
3D Packaging ◽  
Snag Solder ◽  
Current Densities ◽  
Silicon Vias

AbstractCopper is a commonly used interconnect metal in microelectronic interconnects due to its exceptional electrical and thermal properties. Particularly in applications of the 2.5 and 3D integration, Cu is utilized in through-silicon-vias (TSVs) and flip chip interconnects between microelectronic chips for providing miniaturization, lower power and higher performance than current 2D packaging approaches. SnAg capped Cu pillars are a common high-density interconnect technology for flip chip bonding. For these interconnects, specific properties of the Cu surface, such as roughness and cleanliness, are an important factor in the process to ensure quality solder bumps. During electroplating, tight processing parameters must be met so that defects are avoided, and high bump uniformity is achieved. An understanding of the interactions at the solder and Cu pillar interface is needed, based on the electroplating parameters, to determine the best method for populating solder on the wafer surface. In this study, surface treatment techniques such as oxygen plasma cleaning were performed on the Cu surfaces and the SnAg plating chemistry for depositing the solder were evaluated through hull cell testing to qualitatively determine the range of current densities to investigate. It was observed that current density while plating played a large role in solder bump deposition morphology. At the higher current densities greater than 60 mA/cm2, bump height non-uniformity and dendritic growth are observed and at lower current densities, less than or equal to 60 mA/cm2, uniform, continuous bump height occurred.

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