SOLDERABLE ANISOTROPIC CONDUCTIVE ADHESIVES FOR 3D PACKAGE APPLICATIONS

2014 ◽  
Vol 2014 (1) ◽  
pp. 000165-000169
Author(s):  
Mary Liu ◽  
Wusheng Yin
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Low Cost ◽  
Organic Substrate ◽  
Advanced Materials ◽  
Assembly Process ◽  
Conductive Adhesives ◽  
Bump Height ◽  
3D Packaging ◽  
3D Package

3D packaging has recently become very attractive because it can provide more flexibility in device design and supply chain, reduce the gap between silicon die and organic substrate, help miniaturize devices and meet the demand of high speed, provide more memory, more function and low cost. With the advancement of 3D packaging, the bump height is now down from 80μ to 10μ. When the bump diameter is 20–40μ and height 10μ, the process and reliability are obvious issues. It is well known that underfill can enhance the reliability for regular flip chip, however underfill won't help assembly process. In order to resolve some difficulties that 3D packaging faces, YINCAE Advanced Materials, LLC has developed solderable anisotropic conductive adhesives for 3D package applications. In this paper we will discuss the assembly process and reliability in detail.

Underfill For Ultra-Low Bumped (10μ) 3D Package

2010 ◽  
Vol 2010 (1) ◽  
pp. 000786-000791
Author(s):  
Mary Liu ◽  
Wusheng Yin
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Low Cost ◽  
Organic Substrate ◽  
The Other ◽  
Bump Height ◽  
Underfill Flow ◽  
Fast Flow ◽  
Board Level ◽  
3D Package

3D package has recently become very attractive because it can provide more flexibility in device design and supply chain, reduce the gap between silicon die and organic substrate, help miniaturize device and meet the demand of high speed, more memory, more function and low cost. With the advancement of 3D package, the bump height is now down from 80μ to 10 μ. When the bump diameter is 20–40μ and height 10μ, the process and reliability are obvious issues. It is well known that underfill can enhance the reliability for regular flip chip, however it is very difficult for traditional flip chip underfill or board level underfill flow into 10μ multi-layer of 3D package without process and reliability issues. A unique flip chip underfill series has been successfully developed, which not only function as traditional underfill such as flip chip but also work very well for 10μ bump height 3D package application. YINCAE underfill series allow fast flow into 3D package and fast cure. After underfilling and cure, there are no voids observed in underfill. In this paper, a total of four different underfills have been studied. Compared to the other flip chip underfill, YINCAE underfill has demonstrated both excellent workability and outstanding reliability. In terms of workability and reliability, the four different flip chip underfills can be ranked in the following order from best to worst: A underfill > B underfill > C underfill > D underfill.

Thermally Activated Bumping Process using Sn3.0Ag0.5Cu Solder Powder for Low-Cost Interposers

2013 ◽  
Vol 2013 (1) ◽  
pp. 000420-000423
Author(s):  
Kwang-Seong Choi ◽  
Ho-Eun Bae ◽  
Haksun Lee ◽  
Hyun-Cheol Bae ◽  
Yong-Sung Eom
Keyword(s):  
Screen Printing ◽  
Flip Chip ◽  
Solder Bump ◽  
Low Cost ◽  
Organic Substrate ◽  
Lead Free ◽  
Lead Free Solder ◽  
Thermally Activated ◽  
Fine Pitch ◽  
Free Solder

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

Evaluation of a Conductive Adhesive Based Approach to Lead Free Flip Chip Assembly

2002 ◽  
Author(s):  
Muthiah Venkateswaran ◽  
Peter Borgesen ◽  
K. Srihari
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Critical Evaluation ◽  
Conductive Adhesive ◽  
Circuit Board ◽  
Lead Free ◽  
Conductive Adhesives ◽  
Flip Chip Assembly ◽  
Placement Machine

Electrically conductive adhesives are emerging as a lead free, flux less, low temperature alternative to soldering in a variety of electronics and optoelectronics applications. Some of the potential benefits are obvious, but so far the adhesives have some limitations as well. The present work offers a critical evaluation of one approach to flip chip assembly, which lends itself particularly well to use with a high speed placement machine. Wafers were bumped by stencil printing of a thermoset conductive adhesive, which was then fully cured. In assembly, the conductive adhesive paste was stencil printed onto the pads of a printed circuit board and cured after die placement. The printing process was optimized to ensure robust assembly and the resulting reliability assessed.

Advanced TSV Filling Technology for 3-Dimensional Electronic Packaging

2014 ◽  
Vol 783-786 ◽  
pp. 2758-2764
Author(s):  
Chang Woo Lee ◽  
Young Ki Ko ◽  
Yong Ho Ko ◽  
Jung Hwan Bang
Keyword(s):  
High Speed ◽  
Composite Solder ◽  
High Reliability ◽  
Low Cost ◽  
Molten Solder ◽  
Electronic Systems ◽  
Filling Material ◽  
3 Dimensional ◽  
Cu Pillar Bump ◽  
3D Packaging

The development of 3D integration is necessarily required for high speed, high density, small size, and multi-functional electronic devices. Through silicon via (TSV) technology has been rapidly developed to fulfill the demand of the next generation of multifunctional electronic systems as one of the most alternative applications for 3D packaging. In this study, low cost and high speed molten solder-filling of TSV and bonding process by using micro bump was investigated. Micro bumps were formed with two step, Cu pillar bump and Sn-Ag cap bump by using electroplating. The size of micro-bumps was 10 and 20um and the precise content of the bump was developed with good planarity by adding reflow process. Additionally, the SiC nanoparticle composite solder was fabricated for low CTE filling material. From the results, it is possible that the CTE of composite solder added 1.0wt% SiC nanoparticles had decreased until 15.0ppm/°C. Comparing CTE of pure Sn, which was about 24.0ppm/°C, it was very low CTE and lower then CTE of Cu (16.5ppm/°C). Even if the electrical resistance of nanopowder composite solder is increased, the increasing rate is very slow until 1.0 wt%. However, the resistance changing rate is rapidly increased over the 1.0wt%. From the result, it is expected that nanopowder composite solder can contribute high reliability of molten solder filling TSV.

Coreless Substrate Design, Assembly and Reliability for High Speed Applications

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001486-001513
Author(s):  
Jon Aday ◽  
Nozad Karim ◽  
Mike Devita ◽  
Steven Lee
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Core Layer ◽  
Power Delivery ◽  
Advanced Materials ◽  
Band Width ◽  
Electrical Performance ◽  
Next Generation ◽  
Reliability Data ◽  
The Core

There are 2 primary drivers for advanced substrate technologies to support the next generation of products. One driver is silicon designs which are shifting to 20–40 GBit applications. The band width of these products are requiring advanced materials, and designs which use much thinner cores making routing and manufacturing of these packages easier. The second driver is the move more advanced silicon nodes which also drives the importance for much better power delivery. Coreless substrates enable both of these applications by eliminating the core layer which enables much finner via pitchs to route signals and power/gnd planes. The thinness also reduces the bandwidth used up by the substrate which also enables better electrical performance. This paper will focus on the electrical drivers including simulation to support the structure, flip chip assembly of the package as well as the reliability data associated with the assembly.

scholarly journals Flip Chip integration of ultra-thinned dies in low-cost flexible printed electronics; the effects of die thickness, encapsulation and conductive adhesives

2021 ◽  
Vol 123 ◽  
pp. 114204
Author(s):  
Muhammad Hassan Malik ◽  
Giovanna Grosso ◽  
Hubert Zangl ◽  
Alfred Binder ◽  
Ali Roshanghias
Keyword(s):  
Flip Chip ◽  
Printed Electronics ◽  
Low Cost ◽  
Conductive Adhesives ◽  
Die Thickness
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