Characteristics of All-Omcvd Grown GaAs Mesfets on Si Substrates

1988 ◽  
Vol 116 ◽  
Author(s):  
Jhang Woo Lee ◽  
R. E. McCullough ◽  
R. H. Morrison
Keyword(s):  
Leakage Current ◽  
Breakdown Voltage ◽  
Buffer Layers ◽  
Low Background ◽  
Si Substrates ◽  
Turn On ◽  
Gaas Mesfet ◽  
Dc Characteristics ◽  
Key Factor ◽  
Background Doping

AbstractWe present DC characteristics of all-OMCVD grown GaAs MESFET structures on Si substrates with unintentionally doped GaAs or AlGaAs buffer layers. MESFETs fabricated in two and three inch GaAs on Si wafers pinch off well and exhibit reasonably high transconductances up to 110 mS/mm for 1 µm gate devices. The reverse Schottky breakdown voltage of the MESFET gate is as high as 15 V and the forward turn on voltage is ~0.65 V. The ohmic isolation is comparable to the typical homoepitaxial layer with a leakage current of 100 nA at a I V bias. The low background doping levels of unintentionally doped GaAs buffer layers is the key factor for this successful MESFET operation.

Characteristics of all-OMCVD Grown GaAs MESFETS on Si Substrates

1988 ◽  
Vol 126 ◽  
Author(s):  
Jhang Woo Lee ◽  
R. M. McCullough ◽  
R. H. Morrison
Keyword(s):  
Leakage Current ◽  
Breakdown Voltage ◽  
Buffer Layers ◽  
Low Background ◽  
Si Substrates ◽  
Turn On ◽  
Gaas Mesfet ◽  
Dc Characteristics ◽  
Key Factor ◽  
Background Doping

ABSTRACTWe present DC characteristics of all-OMCVD grown GaAs MESFET structures on Si substrates with unintentionally doped GaAs or AlGaAs buffer layers. MESFETs fabricated in two and three inch GaAs on Si wafers pinch off well and exhibit reasonably high transconductances up to 110 mS/mm for 1 μm gate devices. The reverse Schottky breakdown voltage of the MESFET gate is as high as 15 V and the forward turn on voltage is ∼0.65 V. The ohmic isolation is comparable to the typical homoepitaxial layer with a leakage current of 100 nA at a 1 V bias. The low background doping levels of unintentionally doped GaAs buffer layers is the key factor for this successful MESFET operation.

Effects of Silicon Misorientation Angle on the Rf and Dc Characteristics of GaAs-on-Si Mesfets

1995 ◽  
Vol 379 ◽  
Author(s):  
Christos Papavassiliou ◽  
G. Constantinidis ◽  
N. Kornilios ◽  
A. Georgakilas ◽  
E. LÖchterman ◽  
...  
Keyword(s):  
Misorientation Angle ◽  
Defect Density ◽  
Initial Study ◽  
Buffer Layers ◽  
Silicon Substrates ◽  
Heteroepitaxial Growth ◽  
Mbe Growth ◽  
Gaas Mesfet ◽  
Gaas On Si ◽  
Dc Characteristics

ABSTRACTA systematic experimental investigation has been undertaken for the optimization of the wafer parameters and processing for silicon wafers intended for use as substrates for MBE growth, with emphasis on heteroepitaxial growth of GaAs-on- Si. Within this investigation, results are presented of an initial study focused on the optimization of the magnitude of the misorientation angle towards a <110> direction for the growth of GaAs on (001) Si wafers. This angle controls the structure of the stepped (001)Si surface and can influence the defect density and surface smoothness of the GaAs-on-Si layers. Silicon substrates misoriented from 0 deg. up to 9 deg. were cut to specification and subsequently used for the epitaxial growth of GaAs MESFET structures. MESFETs were fabricated and their dc and RF characteristics compared. The resistivity of the GaAs-on-Si buffer layers was evaluated and correlated to the results from device characterization. This work presents the effects of the magnitude of the angle of misorientation in the range from 0 to 9 deg.

AlGaN/GaN MIS-HEMTs with a p-GaN Cap Layer

MRS Advances ◽  
2017 ◽  
Vol 3 (3) ◽  
pp. 143-146
Author(s):  
Che-Ching Hsu ◽  
Pei-Chien Shen ◽  
Yi-Nan Zhong ◽  
Yue-Ming Hsin
Keyword(s):  
Leakage Current ◽  
Breakdown Voltage ◽  
Drain Current ◽  
Gate Insulator ◽  
Current Ratio ◽  
Dc Characteristics ◽  
Cap Layer

ABSTRACTIn this study, AlGaN/GaN MIS-HEMTs with a p-GaN cap layer and ALD deposited Al2O3 gate insulator were fabricated. Devices with two different thicknesses of p-GaN cap layers were investigated and compared. AlGaN/GaN MIS-HEMT with an 8-nm p-GaN cap showed a better DC characteristics than device with a 5-nm p-GaN cap. The drain current of 662.9 mA/mm, a high on/off current ratio of 2.67×109 and a breakdown voltage of 672 V were measured in device with an 8-nm p-GaN cap. In addition, lateral leakage current was investigated by using adjacent MIS gate structures with a separation of 3 μm to investigate the leakage current.

scholarly journals A Novel Gate Drive Circuit for Suppressing Turn-on Oscillation of Non-Kelvin Packaged SiC MOSFET

Energies ◽  
2021 ◽  
Vol 14 (9) ◽  
pp. 2449
Author(s):  
Hongyan Zhao ◽  
Jiangui Chen ◽  
Yan Li ◽  
Fei Lin
Keyword(s):  
Thermal Conductivity ◽  
Breakdown Voltage ◽  
Basic Principle ◽  
Double Pulse ◽  
Experimental Results ◽  
Switching Frequency ◽  
Turn On ◽  
Proof Testing ◽  
Gate Driver ◽  
Drive Circuit

Compared with a silicon MOSFET device, the SiC MOSFET has many benefits, such as higher breakdown voltage, faster action speed and better thermal conductivity. These advantages enable the SiC MOSFET to operate at higher switching frequencies, while, as the switching frequency increases, the turn-on loss accounts for most of the loss. This characteristic severely limits the applications of the SiC MOSFET at higher switching frequencies. Accordingly, an SRD-type drive circuit for a SiC MOSFET is proposed in this paper. The proposed SRD-type drive circuit can suppress the turn-on oscillation of a non-Kelvin packaged SiC MOSFET to ensure that the SiC MOSFET can work at a faster turn-on speed with a lower turn-on loss. In this paper, the basic principle of the proposed SRD-type drive circuit is analyzed, and a double pulse platform is established. For the purpose of proof-testing the performance of the presented SRD-type drive circuit, comparisons and experimental verifications between the traditional gate driver and the proposed SRD-type drive circuit were conducted. Our experimental results finally demonstrate the feasibility and effectiveness of the proposed SRD-type drive circuit.

Study of Modulation in GaAs Misfets with LT-GaAs as a Gate Insulator

1991 ◽  
Vol 241 ◽  
Author(s):  
L.-W. Yin ◽  
J. Ibbetson ◽  
M. M. Hashemi ◽  
W. Jiang ◽  
S.-Y. Hu ◽  
...  
Keyword(s):  
Low Temperature ◽  
Gaas Layer ◽  
Gate Insulator ◽  
Gate Bias ◽  
Channel Current ◽  
Turn On ◽  
Dc Characteristics ◽  
Low Temperature Gaas ◽  
Channel Separation ◽  
Lt Gaas

ABSTRACTDC characteristics of a GaAs MISFET structure using low-temperature GaAs (LTGaAs) as the gate insulator were investigated. MISFETs with different gate to channel separation (d) were fabricated. The dependence of four important device parameters such as gate-drain breakdown voltage (VBR), channel current at zero gate bias (Idss), transconductance (gm), and gate-drain turn-on voltage (Von) on the gate insulator thickness were analyzed. It was observed that (a) in terms of Idss and gin, the LT-GaAs gate insulator behaves like an undoped regular GaAs layer and (b) in terms of VBR and Von, the LT-GaAs gate insulator behaves as a trap dominated layer.

Effects of the Sputtering Time of AlN Buffer Layer on the Quality of ZnO Thin Films

2014 ◽  
Vol 881-883 ◽  
pp. 1117-1121 ◽  
Author(s):  
Xiang Min Zhao
Keyword(s):  
Thin Films ◽  
Buffer Layer ◽  
Rf Magnetron Sputtering ◽  
Buffer Layers ◽  
Zno Thin Films ◽  
Zno Films ◽  
Si Substrates ◽  
Atomic Force ◽  
Structure Morphology ◽  
Aln Buffer

ZnO thin films with different thickness (the sputtering time of AlN buffer layers was 0 min, 30 min,60 min, and 90 min, respectively) were prepared on Si substrates using radio frequency (RF) magnetron sputtering system.X-ray diffraction (XRD), atomic force microscope (AFM), Hall measurements setup (Hall) were used to analyze the structure, morphology and electrical properties of ZnO films.The results show that growth are still preferred (002) orientation of ZnO thin films with different sputtering time of AlN buffer layer,and for the better growth of ZnO films, the optimal sputtering time is 60 min.

Epitaxial Growth and Characterization of 4H-SiC(11–20) and (03–38)

2002 ◽  
Vol 742 ◽  
Author(s):  
T. Kimoto ◽  
K. Hashimoto ◽  
K. Fujihira ◽  
K. Danno ◽  
S. Nakamura ◽  
...  
Keyword(s):  
Epitaxial Growth ◽  
Schottky Barrier ◽  
Breakdown Voltage ◽  
Doping Concentration ◽  
Schottky Barrier Diodes ◽  
Homoepitaxial Growth ◽  
Nitrogen Incorporation ◽  
Impurity Doping ◽  
Background Doping

ABSTRACTHomoepitaxial growth, impurity doping, and diode fabrication on 4H-SiC(11–20) and (03–38) have been investigated. Although the efficiency of nitrogen incorporation is higher on the non-standard faces than on (0001), a low background doping concentration of 2∼3×1014 cm-3 can be achieved. On these faces, boron and aluminum are less effectively incorporated, compared to the growth on off-axis (0001). 4H-SiC(11–20) epilayers are micropipe-free, as expected. More interestingly, almost perfect micropipe closing has been realized in 4H-SiC (03–38) epitaxial growth. Ni/4H-SiC(11–20) and (03–38) Schottky barrier diodes showed promising characteritics of 3.36 kV-24 mΩcm2 and 3.28 kV–22 mΩcm2, respectively. The breakdown voltage of 4H-SiC(03–38) Schottky barrier diodes was significantly improved from 1 kV to above 2.5 kV by micropipe closing.

Microstructure and Electrical Properties of ZnO-Pr6O11-Dy2O3-Based Varistor Ceramics Doped with La2O3

2007 ◽  
Vol 336-338 ◽  
pp. 680-683
Author(s):  
Jing Nan Cai ◽  
Yuan Hua Lin ◽  
Rong Juan Zhao ◽  
Ce Wen Nan ◽  
Jin Liang He
Keyword(s):  
Rare Earth ◽  
Phase Composition ◽  
Electrical Properties ◽  
Rare Earth Elements ◽  
Leakage Current ◽  
Breakdown Voltage ◽  
Intergranular Phase ◽  
Ceramic Method ◽  
Sem Micrographs ◽  
Ceramic Samples

ZnO-Pr6O11-Dy2O3-based varistor ceramics doped with 0~1.5 mol% La2O3 were fabricated by a conventional ceramic method. All the samples were sintered at 1350 oCfor 2 h. The phase composition and microstructure of the ceramic samples have been investigated by XRD, SEM and EDS. The results of SEM micrographs indicated that the La2O3 additives can promote ZnO grain’s growth, and the rare earth elements dispersed mainly in the intergranular phase observed by EDS. The electrical properties of the samples determined by the V-I curves revealed that the breakdown voltage of samples decreases from 508 V/mm to about 100 V/mm with the increase of La2O3, and the nonlinear exponent also decreases from 20.2 to 13.2. The typical leakage current is about 10.2 μA for the sample doped with 0.5 mol% La2O3.

Defect Reduction in GaAs Epilayers on Si Substrates Using Strained Layer Superlattices

1987 ◽  
Vol 91 ◽  
Author(s):  
N. El-Masry ◽  
N. Hamaguchi ◽  
J.C.L. Tarn ◽  
N. Karam ◽  
T.P. Humphreys ◽  
...  
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Buffer Layers ◽  
Threading Dislocations ◽  
Defect Reduction ◽  
Strained Layer ◽  
Si Substrates ◽  
Density Of Dislocations ◽  
Strained Layer Superlattice ◽  
Strained Layer Superlattices

ABSTRACTInxGa11-xAs-GaAsl-yPy strained layer superlattice buffer layers have been used to reduce threading dislocations in GaAs grown on Si substrates. However, for an initially high density of dislocations, the strained layer superlattice is not an effective filtering system. Consequently, the emergence of dislocations from the SLS propagate upwards into the GaAs epilayer. However, by employing thermal annealing or rapid thermal annealing, the number of dislocation impinging on the SLS can be significantly reduced. Indeed, this treatment greatly enhances the efficiency and usefulness of the SLS in reducing the number of threading dislocations.

Sign in / Sign up

Export Citation Format

Share Document