Chemorheological Characterization of B-Stage Printed Wiring Board Resins

Author(s):  
CM Tung ◽  
PJ Dynes
Author(s):  
Mark Eblen

Thermal management of flip chip style integrated circuits often relies on thermal conduction through the ceramic package and high lead solder grid array leads into the printed wiring board as the primary path for heat removal. Thermal analysis of this package configuration requires accurate characterization of the sometimes geometrically complex package-to-board interface. Given the unique structure of the Six Sigma column grid array (CGA) interconnect, a detailed finite element submodel was used to numerically derive the effective thermal conductivity with comparisons to a conventional CGA interconnect. Once an effective thermal conductivity value is obtained, the entire interconnect layer can be represented as a fictitious cuboid layer for inclusion in a more traditional “closed-form” thermal resistance calculation. This method allows the package designer a quick and robust method to evaluate initial thermal design study tradeoffs.


1993 ◽  
Vol 115 (4) ◽  
pp. 366-372 ◽  
Author(s):  
G. G. Stefani ◽  
N. S. Goel ◽  
D. B. Jenks

Thermal modeling of Surface Mount Technology (SMT) microelectronics packages is difficult due to the complexity of the printed wiring board (PWB) plates through hole (PTH) structure. A simple, yet powerful finite difference based approach, called EPIC (Equivalent Parameter for Interfacial Cells), for modelling complex 2-D and 3-D geometries with multiple materials is used to model the PTH structure. A technique for computing an effective thermal conductivity for the PWB is presented. The results compare favorably with those from a commercially available finite element package but require far less computer time.


Author(s):  
Donald B. Barker ◽  
Brent M. Mager ◽  
Michael D. Osterman

Shear forces in the interconnects of electronic devices can cause electrical opens, which result in device failure. The shear forces are often caused by the thermal expansion (CTE) mismatch between a component and the printed wiring board (PWB). In this paper, an elastic strength of materials analytic model, which is demonstrated by Vandevelde [21], is used to characterize the interconnect shear force behavior in area array packages. The benefit of modeling the shear forces is that they can be related to the device life, a relationship obtained by converting shear to average stress, which can be converted to strain and used as input in a failure model equation. The most significant characterization that will be presented is that the maximum shear force behavior in the outermost interconnects can be characterized by three distinct regions of maximum shear force behavior.


MRS Bulletin ◽  
2006 ◽  
Vol 31 (6) ◽  
pp. 471-475 ◽  
Author(s):  
Marc Chason ◽  
Daniel R. Gamota ◽  
Paul W. Brazis ◽  
Krishna Kalyanasundaram ◽  
Jie Zhang ◽  
...  

AbstractDevelopments originally targeted toward economical manufacturing of telecommunications products have planted the seeds for new opportunities such as low-cost, large-area electronics based on printing technologies. Organic-based materials systems for printed wiring board (PWB) construction have opened up unique opportunities for materials research in the fabrication of modular electronic systems.The realization of successful consumer products has been driven by materials developments that expand PWB functionality through embedded passive components, novel MEMS structures (e.g., meso-MEMS, in which the PWB-based structures are at the milliscale instead of the microscale), and microfluidics within the PWB. Furthermore, materials research is opening up a new world of printed electronics technology, where active devices are being realized through the convergence of printing technologies and microelectronics.


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