Analytic Characterization of Area Array Interconnect Shear Force Behavior

2002 ◽  
Author(s):  
Donald B. Barker ◽  
Brent M. Mager ◽  
Michael D. Osterman
Keyword(s):  
Shear Force ◽  
Electronic Devices ◽  
Failure Model ◽  
Printed Wiring Board ◽  
Shear Forces ◽  
Area Array ◽  
Maximum Shear Force ◽  
Cte Mismatch ◽  
Wiring Board

Shear forces in the interconnects of electronic devices can cause electrical opens, which result in device failure. The shear forces are often caused by the thermal expansion (CTE) mismatch between a component and the printed wiring board (PWB). In this paper, an elastic strength of materials analytic model, which is demonstrated by Vandevelde [21], is used to characterize the interconnect shear force behavior in area array packages. The benefit of modeling the shear forces is that they can be related to the device life, a relationship obtained by converting shear to average stress, which can be converted to strain and used as input in a failure model equation. The most significant characterization that will be presented is that the maximum shear force behavior in the outermost interconnects can be characterized by three distinct regions of maximum shear force behavior.

Study of Structure and Properties of New Rolling-Cut Shear

2010 ◽  
Vol 146-147 ◽  
pp. 991-995
Author(s):  
Zhi Bing Chu ◽  
Qing Xue Huang ◽  
Zhi Yuan Zhang ◽  
Dan Li
Keyword(s):  
Theoretical Analysis ◽  
Shear Force ◽  
Motion Path ◽  
Negative Bias ◽  
Horizontal Force ◽  
Structure And Properties ◽  
Force Component ◽  
Shear Forces ◽  
Maximum Shear Force ◽  
Force Components

Based on rolling-cut shear simulation, using a kind of single-shaft and double eccentricity rolling-cut shear, which adopts a new structure of asymmetric feature and negative bias, as the calculating model by establishing motion path equation of spatial shear mechanism, comparing with the steel shear forces, link forces and horizontal link force components with or without asymmetric feature, the asymmetric formulation is deduced. Such asymmetric crank structure can decrease horizontal force component between the linkages during rolling-cut process, increase the effective drive force on links while it comes to the maximum shear force, and decrease the extrusion of blade arc on steel edge as well. Theoretical analysis and steel-shearing quality at site indicate that asymmetric and negative bias is an important and efficient way to prolong the lifetime of blade, decrease blade wear, improve shearing quality, and maintain the constant clearance between blades.

Effective Thermal Conductivity of Six Sigma’s Copper Reinforced Column Grid Array Interconnect for Ceramic Microelectronic Packages

2010 ◽  
Author(s):  
Mark Eblen
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuits ◽  
Effective Thermal Conductivity ◽  
Flip Chip ◽  
Heat Removal ◽  
Thermal Design ◽  
Printed Wiring Board ◽  
Wiring Board ◽  
High Lead

Thermal management of flip chip style integrated circuits often relies on thermal conduction through the ceramic package and high lead solder grid array leads into the printed wiring board as the primary path for heat removal. Thermal analysis of this package configuration requires accurate characterization of the sometimes geometrically complex package-to-board interface. Given the unique structure of the Six Sigma column grid array (CGA) interconnect, a detailed finite element submodel was used to numerically derive the effective thermal conductivity with comparisons to a conventional CGA interconnect. Once an effective thermal conductivity value is obtained, the entire interconnect layer can be represented as a fictitious cuboid layer for inclusion in a more traditional “closed-form” thermal resistance calculation. This method allows the package designer a quick and robust method to evaluate initial thermal design study tradeoffs.

An Efficient Numerical Technique for Thermal Characterization of Printed Wiring Boards

1993 ◽  
Vol 115 (4) ◽  
pp. 366-372 ◽  
Author(s):  
G. G. Stefani ◽  
N. S. Goel ◽  
D. B. Jenks
Keyword(s):  
Numerical Technique ◽  
Thermal Characterization ◽  
Computer Time ◽  
Printed Wiring Boards ◽  
Printed Wiring Board ◽  
Equivalent Parameter ◽  
Finite Element Package ◽  
Multiple Materials ◽  
Wiring Board

Thermal modeling of Surface Mount Technology (SMT) microelectronics packages is difficult due to the complexity of the printed wiring board (PWB) plates through hole (PTH) structure. A simple, yet powerful finite difference based approach, called EPIC (Equivalent Parameter for Interfacial Cells), for modelling complex 2-D and 3-D geometries with multiple materials is used to model the PTH structure. A technique for computing an effective thermal conductivity for the PWB is presented. The results compare favorably with those from a commercially available finite element package but require far less computer time.

Warpage Measurement Using Projection Moire´ System and Two Automatic Image Segmentation Algorithms

2007 ◽  
Author(s):  
Wei Tan ◽  
I. Charles Ume
Keyword(s):  
Image Segmentation ◽  
Electronic Packages ◽  
Printed Wiring Board ◽  
Segmentation Algorithms ◽  
Out Of Plane ◽  
Cte Mismatch ◽  
Image Models ◽  
Wiring Board ◽  
Plane Displacement ◽  
Projection Moire

Out-of-plane displacement (warpage) has been a major reliability concern for board-level electronic packaging. Printed wiring board (PWB) and component warpage results from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly reflow processes and normal operations may lead to serious reliability problems. In this paper, a projection moire´ warpage measurement system and two types of automatic image segmentation algorithms were presented. In order to use the projection moire´ technique to separately determine the warpage of a PWB and assembled electronic packages in a PWBA, two image segmentation algorithms based on mask image models and active contour models (snakes) were developed. They were used to detect package locations in a PWBA displacement image generated by the projection moire´ system. The performances of the mask image and snake approaches based on their resolutions, processing rates, and measurement efficiencies were evaluated in this research. Real-time composite Hermite surface models were constructed to estimate the PWB warpage values underneath the electronic packages. The above automatic image segmentation algorithms were integrated with the projection moire´ system to accurately evaluate the warpage of PWBs and assembled chip packages individually.

Experimental and Numerical Study of the Effect of Plastic Ball Grid Array Package Placement on PWB Warpage During Convective Solder Reflow

2006 ◽  
Author(s):  
Reinhard E. Powell ◽  
Wei Tan ◽  
I. Charles Ume
Keyword(s):  
Finite Element ◽  
Electronic Packaging ◽  
Ball Grid Array ◽  
Interfacial Stress ◽  
Printed Wiring Board ◽  
Plastic Ball ◽  
Plastic Ball Grid Array ◽  
Cte Mismatch ◽  
Wiring Board ◽  
Projection Moire

Warpage has long been known to cause thermomechanical reliability problems in electronic packaging. The coefficient of thermal expansion (CTE) mismatch between different materials in an electronic assembly such as solder, copper, FR-4, encapsulation molding, and silicon is known to be one of the leading causes of manufacturing defects and fatigue failures. The CTE mismatch between packaging materials induces thermomechanical stresses at interfaces between the materials. Warpage is a global effect of interfacial stress and displacement. The warpage problem in electronic packaging can be further aggravated by thermal processes such as reflow and temperature cycling. In a printed wiring board assembly (PWBA), warpage of the PWB or chip packages may result in chip package misregistration, solder joint failure, die cracking and delamination of the solder bumps between chip packages and the PWB. In this paper, the warpage of a printed wiring board assembly (PWBA) is studied using projection moire´ experimental measurements and a finite element model. The effects of plastic ball grid array (PBGA) chip package placement on PWB warpage during convective reflow will be evaluated. The projection moire´ experimental warpage results will show that the number of PBGA chip packages as well as their location has an effect on the warpage of the PWB. In addition to the experimental results, the finite element warpage results will be used to make recommendations on the optimal PBGA package placement locations on the PWB to minimize PWB warpage during reflow processes.

Study on CAM System for Drilling in Printed Wiring Boards: Optimization of Stacking Sheet Considering Drill Processing Temperature

2009 ◽  
Author(s):  
Toshiki Hirogaki ◽  
Eiichi Aoyama ◽  
Keiji Ogawa ◽  
Tsuyoshi Okawa
Keyword(s):  
Electronic Devices ◽  
Aramid Fiber ◽  
Processing Temperature ◽  
Processing Quality ◽  
Next Generation ◽  
Fiber Reinforced ◽  
Printed Wiring Boards ◽  
Printed Wiring Board ◽  
Drilling Technology ◽  
Wiring Board

Recently, printed wiring boards (PWBs), which are employed in electronic devices, have been miniaturized, lightened, and made multifunctional. This trend demands the improvement of drilling technology and a method to raise productivity. In this study, as a processing sample, we use the aramid fiber-reinforced printed wiring board (AFRP) of the next generation PWB, which is attracting attention, and GFRP, which is most commonly used. We investigate the processing temperature and the processing quality and conduct number optimization of the sheets to improve productivity by increasing their number.

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