Multilevel Cell Storage and Resistance Variability in Resistive Random Access Memory

2016 ◽  
Vol 1 (6) ◽  
Author(s):  
Amit Prakash ◽  
Hyunsang Hwang
Keyword(s):  
Low Cost ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Comprehensive Analysis ◽  
Multiple Resistance ◽  
Access Memory ◽  
Physical Mechanisms ◽  
Reliability Characteristics ◽  
The Impact

Abstract Multilevel per cell (MLC) storage in resistive random access memory (ReRAM) is attractive in achieving high-density and low-cost memory and will be required in future. In this chapter, MLC storage and resistance variability and reliability of multilevel in ReRAM are discussed. Different MLC operation schemes with their physical mechanisms and a comprehensive analysis of resistance variability have been provided. Various factors that can induce variability and their effect on the resistance margin between the multiple resistance levels are assessed. The reliability characteristics and the impact on MLC storage have also been assessed.

scholarly journals Analysis of Leakage Current of HfO2/TaOx-Based 3-D Vertical Resistive Random Access Memory Array

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 614
Author(s):  
Zhisheng Chen ◽  
Renjun Song ◽  
Qiang Huo ◽  
Qirui Ren ◽  
Chenrui Zhang ◽  
...  
Keyword(s):  
Leakage Current ◽  
Current Model ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Memory Storage ◽  
Access Memory ◽  
Leakage Currents ◽  
The Impact

Three-dimensional vertical resistive random access memory (VRRAM) is proposed as a promising candidate for increasing resistive memory storage density, but the performance evaluation mechanism of 3-D VRRAM arrays is still not mature enough. The previous approach to evaluating the performance of 3-D VRRAM was based on the write and read margin. However, the leakage current (LC) of the 3-D VRRAM array is a concern as well. Excess leakage currents not only reduce the read/write tolerance and liability of the memory cell but also increase the power consumption of the entire array. In this article, a 3-D circuit HSPICE simulation is used to analyze the impact of the array size and operation voltage on the leakage current in the 3-D VRRAM architecture. The simulation results show that rapidly increasing leakage currents significantly affect the size of 3-D layers. A high read voltage is profitable for enhancing the read margin. However, the leakage current also increases. Alleviating this conflict requires a trade-off when setting the input voltage. A method to improve the array read/write efficiency is proposed by analyzing the influence of the multi-bit operations on the overall leakage current. Finally, this paper explores different methods to reduce the leakage current in the 3-D VRRAM array. The leakage current model proposed in this paper provides an efficient performance prediction solution for the initial design of 3-D VRRAM arrays.

Low-cost bidirectional selector based on Ti/TiO2/HfO2/TiO2/Ti stack for bipolar RRAM arrays

2015 ◽  
Vol 29 (35n36) ◽  
pp. 1550244 ◽  
Author(s):  
Yingtao Li ◽  
Rongrong Li ◽  
Peng Yuan ◽  
Xiaoping Gao ◽  
Enzi Chen
Keyword(s):  
Low Cost ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Access Memory ◽  
Good Point ◽  
Good Uniformity ◽  
Switching Characteristics ◽  
The One ◽  
Point Of Reference

In this paper, a low-cost Ti/TiO2/HfO2/TiO2/Ti stack structure is proposed as a selector for bipolar resistive random access memory (RRAM) cross-bar array applications. We demonstrate reproducible resistive switching characteristics with significant nonlinearity and good uniformity in the one selector and one resistor (1S1R) structure device that integrate the bidirectional selector with a bipolar Pt/Ti/HfO2/Pt RRAM device. These results provide a good point of reference for evaluating the potential low-cost applications in bipolar RRAM cross-bar array.

scholarly journals Multiscale Modeling for Application-Oriented Optimization of Resistive Random-Access Memory

Materials ◽  
2019 ◽  
Vol 12 (21) ◽  
pp. 3461 ◽  
Author(s):  
Paolo La Torraca ◽  
Francesco Maria Puglisi ◽  
Andrea Padovani ◽  
Luca Larcher
Keyword(s):  
Neural Networks ◽  
Multiscale Modeling ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Access Memory ◽  
Promising Alternative ◽  
Von Neumann ◽  
Design And Optimization ◽  
Physical Mechanisms

Memristor-based neuromorphic systems have been proposed as a promising alternative to von Neumann computing architectures, which are currently challenged by the ever-increasing computational power required by modern artificial intelligence (AI) algorithms. The design and optimization of memristive devices for specific AI applications is thus of paramount importance, but still extremely complex, as many different physical mechanisms and their interactions have to be accounted for, which are, in many cases, not fully understood. The high complexity of the physical mechanisms involved and their partial comprehension are currently hampering the development of memristive devices and preventing their optimization. In this work, we tackle the application-oriented optimization of Resistive Random-Access Memory (RRAM) devices using a multiscale modeling platform. The considered platform includes all the involved physical mechanisms (i.e., charge transport and trapping, and ion generation, diffusion, and recombination) and accounts for the 3D electric and temperature field in the device. Thanks to its multiscale nature, the modeling platform allows RRAM devices to be simulated and the microscopic physical mechanisms involved to be investigated, the device performance to be connected to the material’s microscopic properties and geometries, the device electrical characteristics to be predicted, the effect of the forming conditions (i.e., temperature, compliance current, and voltage stress) on the device’s performance and variability to be evaluated, the analog resistance switching to be optimized, and the device’s reliability and failure causes to be investigated. The discussion of the presented simulation results provides useful insights for supporting the application-oriented optimization of RRAM technology according to specific AI applications, for the implementation of either non-volatile memories, deep neural networks, or spiking neural networks.

scholarly journals Green thin film for stable electrical switching in a low-cost washable memory device: proof of concept

RSC Advances ◽  
2021 ◽  
Vol 11 (8) ◽  
pp. 4327-4338
Author(s):  
Naila Arshad ◽  
Muhammad Sultan Irshad ◽  
Misbah Sehar Abbasi ◽  
Saif Ur Rehman ◽  
Iftikhar Ahmed ◽  
...  
Keyword(s):  
Thin Film ◽  
Resistive Switching ◽  
Low Cost ◽  
Random Access ◽  
Random Access Memory ◽  
Memory Device ◽  
Resistive Random Access Memory ◽  
Proof Of Concept ◽  
Access Memory ◽  
Electrical Switching

Low-cost and washable resistive switching (RS) memory devices with stable retention and low operational voltage are important for resistive random-access memory (RRAM).

The Impact of RTN Signal on Array Level Resistance Fluctuation of Resistive Random Access Memory

2018 ◽  
Vol 39 (5) ◽  
pp. 676-679 ◽  
Author(s):  
Danian Dong ◽  
Jing Liu ◽  
Yuduo Wang ◽  
Xiaoxin Xu ◽  
Peng Yuan ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Access Memory ◽  
The Impact ◽  
Level Resistance

Effect of Conductive Filament Temperature on ZrO2 based Resistive Random Access Memory Devices

2020 ◽  
Vol 12 (2) ◽  
pp. 02008-1-02008-4
Author(s):  
Pramod J. Patil ◽  
◽  
Namita A. Ahir ◽  
Suhas Yadav ◽  
Chetan C. Revadekar ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Memory Devices ◽  
Access Memory ◽  
Conductive Filament ◽  
Filament Temperature

scholarly journals Improved Device Distribution in High-Performance SiNx Resistive Random Access Memory via Arsenic Ion Implantation

Nanomaterials ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 1401
Author(s):  
Te Jui Yen ◽  
Albert Chin ◽  
Vladimir Gritsenko
Keyword(s):  
High Performance ◽  
Conduction Mechanism ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Switching Behavior ◽  
Access Memory ◽  
Current Voltage ◽  
Current Voltage Characteristics ◽  
Limited Conduction

Large device variation is a fundamental challenge for resistive random access memory (RRAM) array circuit. Improved device-to-device distributions of set and reset voltages in a SiNx RRAM device is realized via arsenic ion (As+) implantation. Besides, the As+-implanted SiNx RRAM device exhibits much tighter cycle-to-cycle distribution than the nonimplanted device. The As+-implanted SiNx device further exhibits excellent performance, which shows high stability and a large 1.73 × 103 resistance window at 85 °C retention for 104 s, and a large 103 resistance window after 105 cycles of the pulsed endurance test. The current–voltage characteristics of high- and low-resistance states were both analyzed as space-charge-limited conduction mechanism. From the simulated defect distribution in the SiNx layer, a microscopic model was established, and the formation and rupture of defect-conductive paths were proposed for the resistance switching behavior. Therefore, the reason for such high device performance can be attributed to the sufficient defects created by As+ implantation that leads to low forming and operation power.

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