scholarly journals Design techniques for low-voltage analog integrated circuits

2017 ◽  
Vol 68 (4) ◽  
pp. 245-255 ◽  
Author(s):  
Matej Rakús ◽  
Viera Stopjaková ◽  
Daniel Arbet
Keyword(s):  
Integrated Circuits ◽  
Low Voltage ◽  
Supply Voltage ◽  
Building Blocks ◽  
Cmos Process ◽  
Mos Transistors ◽  
Power Supply Voltage ◽  
Current Mirrors ◽  
Moderate Inversion ◽  
Design Techniques

AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

scholarly journals Low-voltage, low-power and high gain cmosota using active positive feedback with feed forward and FDCM techniques

2002 ◽  
Vol 15 (1) ◽  
pp. 93-101
Author(s):  
Lyes Bouzerara ◽  
Tahar Belaroussi ◽  
Boualem Amirouche
Keyword(s):  
Positive Feedback ◽  
Low Voltage ◽  
Supply Voltage ◽  
Phase Margin ◽  
Current Mirror ◽  
Power Supply Voltage ◽  
Gain Bandwidth ◽  
Frequency Dependent ◽  
Feed Forward ◽  
Current Mirrors

A low voltage, high dc gain and wideband load compensated cas code operational transconductance amplifier (OTA), using an active positive feedback with feed forward technique and frequency-dependent current mirrors (FDCM), is presented and analyzed. Such techniques stand as a powerful method of gain bandwidth and phase margin enhancements. In this paper, a frequency-dependent current mirror, whose input impedance increases with frequency, is used to form the feed forward path at the input of the current mirror with a feed forward capacitor. By using these techniques, the gain bandwidth product of the amplifier is improved from 115 MHz to 194 MHz, the phase margin is also improved from 85? to 95? and the gain is enhanced from 11 dB to 93 dB. This amplifier operates at 2.5 V power supply voltage drives a capacitive load of 1pF and gives a power dissipation of 7 mW. The predicted performance is verified by simulations using HSPICE tool with 0.8 fim CMOS AMS parameters.

A High-Speed Fully Differential Telescopic Op-Amp for Active Filter Designs in V2X Applications

2021 ◽  
Author(s):  
Furkan Barin ◽  
Ertan Zencir
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Active Filter ◽  
Ultra Wideband ◽  
Two Stage ◽  
Fully Differential ◽  
Op Amp ◽  
Current Mirrors ◽  
Design Techniques

In this paper, an ultra-wideband fully differential two-stage telescopic 65-nm CMOS op-amp is presented, which uses low-voltage design techniques such as level shifter circuits and low-voltage cascode current mirrors. The designed op-amp consists of two stages. While the telescopic first stage provides high speed and low swing, the second stage provides high gain and large swing. Common-mode feedback circuits (CMFB), which contain five transistors OTA and sensing resistors, are used to set the first-stage output to a known value. The designed two-stage telescopic operational amplifier has 41.04[Formula: see text]dB lower frequency gain, 1.81[Formula: see text]GHz gain-bandwidth product (GBW) and 51.9∘ phase margin under 5[Formula: see text]pF load capacitance. The design consumes a total current of 11.9[Formula: see text]mA from a 1.2-V supply voltage. Presented fully differential two-stage telescopic op-amp by using low-voltage design techniques is suitable for active filter in vehicle-to-everything (V2X) applications with 120[Formula: see text][Formula: see text]m[Formula: see text]m layout area.

scholarly journals Low-voltage 0.35-/mi cmos wideband operational transconductance amplifier

2002 ◽  
Vol 15 (3) ◽  
pp. 361-369
Author(s):  
Lyes Bouzerara ◽  
Mohand Belaroussi
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Output Impedance ◽  
Power Supply Voltage ◽  
Gain Bandwidth ◽  
Current Mirrors ◽  
Transconductance Amplifier ◽  
Cascade Structure ◽  
Feedback Frequency ◽  
High Output Impedance

A low voltage CMOS wideband operational Tran conductance amplifier (OTA) using regulated cascade structure with an active positive feedback frequency-dependent current mirrors and feed forward techniques, is presented and analyzed. Such techniques stand as a powerful method of gain bandwidth, output impedance and phase margin enhancements. In this paper, an efficient implementation of a high output impedance current mirror is used in the design of an OTA by means of the regulated cascade circuits. This amplifier operates at ?1.25 V power supply voltage, exhibits a voltage gain of 68 dB, and provides a gain bandwidth product of 166 MHz. It drives a capacitive load of 1.6 pF and gives a power dissipation of 8.5 mW. The predicted performance is verified by simulations using HSPICE tool with 0.35 /itm CMOS TSMC parameters.

scholarly journals A 0.6 V MOS-Only Voltage Reference for Biomedical Applications with 40 ppm/∘C Temperature Drift

2018 ◽  
Vol 27 (08) ◽  
pp. 1850128 ◽  
Author(s):  
R. Nagulapalli ◽  
K. Hayatleh ◽  
Steve Barker ◽  
Sumathi Raparthy ◽  
Nabil Yassine ◽  
...  
Keyword(s):  
Power Supply ◽  
Biomedical Applications ◽  
Low Voltage ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Mos Transistors ◽  
Power Supply Voltage ◽  
Temperature Drift ◽  
Ultra Low Power

This paper exploits the CMOS beta multiplier circuit to synthesize a temperature-independent voltage reference suitable for low voltage and ultra-low power biomedical applications. The technique presented here uses only MOS transistors to generate Proportional To Absolute Temperature (PTAT) and Complimentary To Absolute Temperature (CTAT) currents. A self-biasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65[Formula: see text]nm CMOS has been developed and occupies 0.0039[Formula: see text]mm2, and at room temperature, it generates a 204[Formula: see text]mV reference voltage with 1.3[Formula: see text]mV drift over a wide temperature range (from [Formula: see text]40[Formula: see text]C to 125[Formula: see text]C). This has been designed to operate with a power supply voltage down to 0.6[Formula: see text]V and consumes 1.8[Formula: see text]uA current from the supply. The simulated temperature coefficient is 40[Formula: see text]ppm/[Formula: see text]C.

scholarly journals Challenges of <i>V</i><i><sub>DD</sub></i> scaling for analog circuits: an amplifier

2005 ◽  
Vol 3 ◽  
pp. 377-381
Author(s):  
A. Bargagli-Stoffi ◽  
J. Sauerbrey ◽  
J. Wang ◽  
D. Schmitt-Landsiedel
Keyword(s):  
Power Supply ◽  
Analog Circuits ◽  
Low Voltage ◽  
Supply Voltage ◽  
Analog Design ◽  
Power Supply Voltage ◽  
Current Mirrors ◽  
Satisfactory Performance ◽  
Transconductance Amplifier ◽  
The Many

Abstract. With the shrinking of the device dimensions, the power supply voltage value is continuously decreasing. Since the threshold voltage value does not decrease as much as the power supply and the drain source saturation voltage becomes an important fraction of the power supply, many amplifier architectures are no more suitable for modern processes. A transconductance amplifier based on current mirrors is analyzed highlighting the main challenges of a low-voltage analog design. Among the many proposed amplifier architectures, a topology based on current mirrors has been chosen as the most promising to operate with low voltages. Simulations with 90nm CMOS prove the feasibility of circuit operation with satisfactory performance at an operating power supply voltage as low as 0.6V.

A Cyclic RSD Analog-Digital-Converter for Application Specific High Temperature Integrated Circuits up to 250°C

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000214-000219 ◽  
Author(s):  
Alexander Schmidt ◽  
Holger Kappert ◽  
Wolfgang Heiermann ◽  
Rainer Kokozinski
Keyword(s):  
Integrated Circuits ◽  
Elevated Temperatures ◽  
Supply Voltage ◽  
Building Blocks ◽  
Cmos Process ◽  
Digital Converter ◽  
Voltage Range ◽  
Temperature Range ◽  
The Impact ◽  
Soi Cmos

Silicon-on-Insulator (SOI) CMOS is the most commonly used technology for integrated circuits suitable for high temperatures and harsh environmental conditions. Data acquisition circuitry operating at these conditions has to consider the impact of wide temperature range operation. Therefore, the accurate operation of elementary building blocks is essential for proper system performance. To overcome the accuracy limitations set by channel leakage and performance degradation of NMOS and PMOS transistors, advanced circuit design methods are necessary. By introducing advanced leakage compensation, the overall performance of analog circuits at elevated temperatures is significantly improved. In this paper we present a cyclic analog-to-digital converter with a resolution of 12 bit, fabricated in a 1.0 μm SOI CMOS process. It utilizes the redundant signed digit (RSD) principle in a switched capacitor circuit and is thus insensitive to amplifier or comparator offset. In order to reduce the conversion error, leakage current compensated switches have been used. The ADC features two high gain operational amplifiers. Thereby a gain of more than 110 dB over the whole temperature range has been realized. The ADC's performance has been verified up to 250°C with an input voltage range from 0 V to 5 V. Preliminary results report an accuracy of more than 10 bits with a conversion rate of 1.25 kS/s. The supply voltage is 5 V with a maximum power consumption of 3.4 mW for the analog part of the circuit. The ADC is intended as an IP module to be used in customer specific mixed signal integrated circuits.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

scholarly journals Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference

2021 ◽  
Vol 11 (1) ◽  
pp. 6
Author(s):  
Orazio Aiello
Keyword(s):  
Integrated Circuits ◽  
Electromagnetic Interference ◽  
Low Voltage ◽  
Current Source ◽  
Building Blocks ◽  
Cmos Technology ◽  
Threshold Region ◽  
Output Current ◽  
Current Generator ◽  
Technology Process

The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Design of the variable frequency oscillator in DC-DC converter

Circuit World ◽  
2019 ◽  
Vol 45 (2) ◽  
pp. 80-85
Author(s):  
Tian Lei ◽  
Nan Gong ◽  
Li Wang ◽  
Qin Qin Li ◽  
Heng Wei Wang
Keyword(s):  
Supply Voltage ◽  
Operating Frequency ◽  
Maximum Deviation ◽  
Variable Frequency ◽  
Cmos Process ◽  
Power Supply Voltage ◽  
Output Stage ◽  
Content Type ◽  
Oscillator Frequency ◽  
Light Load

Purpose Because of the logic delay in the converter, the minimum turn on time of the switch is influenced by the constant time. When the inductor current gets to the threshold of the chip, the control signal will delay for a period. This makes the inductor current rising with the increasing of the clock and leads to the load current out of control. Thus, this paper aims to design an oscillator with a variable frequency protection function. Design/methodology/approach This paper presents an oscillator with the reducing frequency applied in the DC-DC converter. When the converter works normally, the operating frequency of the oscillator is 1.5 MHz. So the inductor current has enough time to decay and prevent the power transistor damaging. After the abnormal condition, the converter returns to the normal operating mode automatically. Findings Based on 0.5 µm CMOS process, simulated by the HSPICE, the simulation results shows that the frequency of the oscillator linearly decreases from 1.5 MHz to 380 KHz when the feedback voltage less than 0.2 V. The maximum deviation of the oscillator frequency is only 6 per cent from −50°C to 125°C within the power supply voltage of 2.7-5.5 V. Originality/value When the light load occurs at the output stage, the oscillator frequency will decrease as the load voltage drops. The test results shows that when the circuit works in the normal condition, the oscillator frequency is 1.5 MHz. When the load decreased, the operating frequency is dropped dramatically.

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