A Cyclic RSD Analog-Digital-Converter for Application Specific High Temperature Integrated Circuits up to 250°C

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000214-000219 ◽  
Author(s):  
Alexander Schmidt ◽  
Holger Kappert ◽  
Wolfgang Heiermann ◽  
Rainer Kokozinski
Keyword(s):  
Integrated Circuits ◽  
Elevated Temperatures ◽  
Supply Voltage ◽  
Building Blocks ◽  
Cmos Process ◽  
Digital Converter ◽  
Voltage Range ◽  
Temperature Range ◽  
The Impact ◽  
Soi Cmos

Silicon-on-Insulator (SOI) CMOS is the most commonly used technology for integrated circuits suitable for high temperatures and harsh environmental conditions. Data acquisition circuitry operating at these conditions has to consider the impact of wide temperature range operation. Therefore, the accurate operation of elementary building blocks is essential for proper system performance. To overcome the accuracy limitations set by channel leakage and performance degradation of NMOS and PMOS transistors, advanced circuit design methods are necessary. By introducing advanced leakage compensation, the overall performance of analog circuits at elevated temperatures is significantly improved. In this paper we present a cyclic analog-to-digital converter with a resolution of 12 bit, fabricated in a 1.0 μm SOI CMOS process. It utilizes the redundant signed digit (RSD) principle in a switched capacitor circuit and is thus insensitive to amplifier or comparator offset. In order to reduce the conversion error, leakage current compensated switches have been used. The ADC features two high gain operational amplifiers. Thereby a gain of more than 110 dB over the whole temperature range has been realized. The ADC's performance has been verified up to 250°C with an input voltage range from 0 V to 5 V. Preliminary results report an accuracy of more than 10 bits with a conversion rate of 1.25 kS/s. The supply voltage is 5 V with a maximum power consumption of 3.4 mW for the analog part of the circuit. The ADC is intended as an IP module to be used in customer specific mixed signal integrated circuits.

scholarly journals Design techniques for low-voltage analog integrated circuits

2017 ◽  
Vol 68 (4) ◽  
pp. 245-255 ◽  
Author(s):  
Matej Rakús ◽  
Viera Stopjaková ◽  
Daniel Arbet
Keyword(s):  
Integrated Circuits ◽  
Low Voltage ◽  
Supply Voltage ◽  
Building Blocks ◽  
Cmos Process ◽  
Mos Transistors ◽  
Power Supply Voltage ◽  
Current Mirrors ◽  
Moderate Inversion ◽  
Design Techniques

AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

scholarly journals CMOS Voltage Reference using a Self-Cascode Composite Transistor and a Schottky Diode

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1271
Author(s):  
Brito ◽  
Colombo ◽  
Moreno ◽  
El-Sankary
Keyword(s):  
Schottky Diode ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Silicon Area ◽  
Circuit Topology ◽  
Voltage Range ◽  
Self Cascode ◽  
Cmos Voltage Reference ◽  
The Impact

This work presents an investigation of the temperature behavior of self-cascode composite transistors (SCCTs). Results supported by silicon measurements show that SCCTs can be used to generate a proportional to absolute temperature voltage or even a temperature-compensated voltage. Based on the achieved results, a new circuit topology of a resistorless voltage reference circuit using a Schottky diode is also presented. The circuit was fabricated in a 130 nm BiCMOS process and occupied a silicon area of 67.98 µm × 161.7 µm. The averaged value of the output voltage is 720.4 mV, and its averaged line regulation performance is 2.3 mV/V, calculated through 26 characterized chip samples. The averaged temperature coefficient (TC) obtained through five chip samples is 56 ppm/°C in a temperature range from −40 to 85°C. A trimming circuit is also included in the circuit topology to mitigate the impact of the fabrication process effects on its TC. The circuit operates with a supply voltage range from 1.1 to 2.5 V.

A 10-Bit Column-Parallel Single Slope ADC Based on Two-Step TDC with Error Calibration for CMOS Image Sensors

2015 ◽  
Vol 24 (04) ◽  
pp. 1550054 ◽  
Author(s):  
Jiangtao Xu ◽  
Jing Yu ◽  
Fujun Huang ◽  
Kaiming Nie
Keyword(s):  
Analog Circuits ◽  
High Speed ◽  
Propagation Delay ◽  
Image Sensors ◽  
Time Interval ◽  
Cmos Process ◽  
Digital Converter ◽  
Cmos Image Sensors ◽  
Time Problem ◽  
The Impact

This paper presents a 10-bit column-parallel single slope analog-to-digital converter (SS ADC) with a two-step time-to-digital converter (TDC) to overcome the long conversion time problem in conventional SS ADC for high-speed CMOS image sensors (CIS). The time interval proportional to the input signal is generated by a ramp generator and a comparator, which is digitized by a two-step TDC consisting of coarse and fine conversions to achieve a high-precision time-interval measurement. To mitigate the impact of propagation delay mismatch, a calibration circuit is also proposed to calibrate the delay skew within -T/2 to T/2. The proposed ADC is designed in 0.18 μm CMOS process. The power dissipation of each column circuit is 232 μW at supply voltages of 3.3 V for the analog circuits and 1.8 V for the digital blocks. The post simulation results indicate that the ADC achieves a SNDR of 60.89 dB (9.82 ENOB) and a SFDR of 79.98 dB at a conversion rate of 2 MS/s after calibration, while the SNDR and SFDR are limited to 41.52 dB and 67.64 dB, respectively before calibration. The differential nonlinearity (DNL) and integral nonlinearity (INL) without calibration are +15.80/-15.29 LSB and +1.68/-15.34 LSB while they are reduced down to +0.75/-0.25 LSB and +0.76/-0.78 LSB with the proposed calibration.

DESIGN OF A CMOS BANDGAP REFERENCE CIRCUIT WITH A WIDE TEMPERATURE RANGE, HIGH PRECISION AND LOW TEMPERATURE COEFFICIENT

2014 ◽  
Vol 23 (08) ◽  
pp. 1450107 ◽  
Author(s):  
JUN-DA CHEN ◽  
CHENG-KAI YE
Keyword(s):  
Temperature Coefficient ◽  
High Precision ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Reference ◽  
Temperature Range ◽  
Wide Range ◽  
Bandgap Voltage Reference ◽  
Reference Circuit ◽  
Cmos Voltage Reference

This paper presents an approach to the design of a high-precision CMOS voltage reference. The proposed circuit is designed for TSMC 0.35 μm standard CMOS process. We design the first-order temperature compensation bandgap voltage reference circuit. The proposed post-simulated circuit delivers an output voltage of 0.596 V and achieves the reported temperature coefficient (TC) of 3.96 ppm/°C within the temperature range from -60°C to 130°C when the supply voltage is 1.8 V. When simulated in a smaller temperature range from -40°C to 80°C, the circuit achieves the lowest reported TC of 2.09 ppm/°C. The reference current is 16.586 μA. This circuit provides good performances in a wide range of temperature with very small TC.

РАЗРАБОТКА И ИССЛЕДОВАНИЕ СВЕТОДИОДНОГО ДРАЙВЕРА

2020 ◽  
Vol 96 (3s) ◽  
pp. 631-634
Author(s):  
О.Л. Климов ◽  
С.М. Игнатьев ◽  
И.В. Ермаков
Keyword(s):  
Research And Development ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Output Current ◽  
Led Driver ◽  
Voltage Range ◽  
Temperature Range ◽  
Current Consumption ◽  
Current Error

Представлены результаты разработки и исследования светодиодного драйвера в КМОП-технологии уровня 0,6 мкм. Погрешность выходного тока драйвера с учетом технологического разброса в диапазоне напряжений питания от 4 до 20 В и диапазоне температур от -60 до +125 °С составила менее ±5 % от номинального значения 3,55 мА. Ток потребления драйвера - менее 100 мкА, а занимаемая площадь - 0,3 х 0,3 мм2. The paper presents the research and development of the LED driver in 0.6 μm CMOS technology. When the supply voltage range is from 4 to 20 V and temperature range is from -60 to +125 °C the output current error of the LED driver taking into account the process corners is less than ±5 % of the nominal value 3.55 mA. The LED driver current consumption is less than 100 uA and the area is less than 0.3 х 0.3 mm2.

Overview of High Performance Packaging Materials

1990 ◽  
Vol 203 ◽  
Author(s):  
Barry C. Johnson
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Building Blocks ◽  
Electrical Performance ◽  
Electronic Systems ◽  
Circuit Performance ◽  
Signal Velocity ◽  
Semiconductor Chip ◽  
Thermal Cooling ◽  
The Impact

ABSTRACTHigh Performance Integrated Circuits form the basic building blocks of modern electronic systems that are designed to process ever larger numbers of electrical signals at greater signal velocity and fidelity. In such applications, each circuit must be packaged in order to provide it with necessary mechanical support, environmental protection, electrical interconnection and thermal cooling. The package, however, can also impose certain constraints on the chip. It can degrade electrical performance, add size and weight, introduce reliability problems and increase cost. Thus, packaging can be viewed as a complex balance between the provision of desired functions and the reduction of associated constraints.The ability to strike a proper balance has become increasingly difficult in recent years due to the relentless march of integrated circuits toward higher levels of complexity, size, speed, heat flux and customization. It is anticipated that the continuing evolution of high performance circuits and systems will soon be limited by the package designs and materials-of-construction, rather than by the devices on the semiconductor chip.The intent of this talk is to provide a brief overview of high performance packaging and the related materials issues. The approach is to (a) present the forecasted trends in relevant circuit performance characteristics, (b) discuss the impact of these characteristics on current chip and board level packaging methods, and (c) present new package and materials concepts that might furnish potential solutions to the developing circuit-package performance gap.

A VERY LOW-TC SECOND-ORDER TEMPERATURE-COMPENSATED CMOS CURRENT REFERENCE

2014 ◽  
Vol 23 (03) ◽  
pp. 1450042 ◽  
Author(s):  
LIANG LIANG ◽  
ZHANGMING ZHU ◽  
YINTANG YANG
Keyword(s):  
Temperature Compensation ◽  
Supply Voltage ◽  
Design Method ◽  
Current Source ◽  
Second Order ◽  
Cmos Process ◽  
Current Mirror ◽  
First Order ◽  
Temperature Range ◽  
Current Reference

This paper proposes a novel second-order temperature-compensated CMOS current reference which exploits a new self-biased current source for first-order temperature compensation and a resistor-free widlar current mirror for second-order temperature compensation. Moreover, by deriving the temperature coefficient (TC) of the reference current, the temperature compensation condition equations together with a design method of minimizing the thermal drift in a required temperature range are presented. Based on these, the circuit is designed in a standard 0.18 μm CMOS process and achieves a very low TC of only 16.9 ppm/°C in a temperature range between -40°C and 120°C, with 1 μA reference current at 27°C. Besides, the current reference can operate at supply voltage down to 1.3 V, with a good supply regulation of 0.5%/V. At 27°C, its power consumption is 8.93 μW.

scholarly journals VERY LARGE SCALE INTEGRATION TINY CHIP WITH NANOPOWER SENSOR APPLICATIONS

2012 ◽  
pp. 116-120
Author(s):  
K.JAYA SWAROOP ◽  
M.I. SUDHARAYAPPA ◽  
CH. JAYAPRAKASH ◽  
V.SURENDRA BABU
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Large Scale ◽  
Supply Voltage ◽  
Vlsi Design ◽  
Electrical Characterization ◽  
Cmos Process ◽  
Process Technology ◽  
Voltage Range ◽  
Sensor Applications

Semiconductor devices have rapidly advanced over the past years increasing switching(on and off) speed and density of the device, causing an increase in power consumption and power dissipation; accordingly, the issues have been considered and improved . In CMOS 0.5μm process, the designed VLSI mirror-amplifier had power dissipation of 8.41 milliwatts. This technique is changed in this paper. The biasing is done in two steps proved to be correct procedure to improve overall power consumption. Source voltage was considered as 3V for the MOSIS process technology. Layout ,simulation and electrical characterization of the design were carried out by MENTOR GRAPHICS tool and CAD tools were used for the design Holding the scaling and process unchanged at 0.5μm as the previous design, the new VLSI design had power dissipation of 4.39 nanowatts in second step by reducing the dynamic loss. Multi-die chip placement is done for fabrication. More advanced 0.35um CMOS process is used for low threshold voltage and enhanced supply voltage range. This paper presents details of the key research works, results, completed chip layout and applications of the chip.

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