scholarly journals EXPERT SYSTEMS AND TEST PLAN GENERATION

1990 ◽  
Author(s):  
ΙΩΑΝΝΗΣ ΠΑΠΑΒΑΣΙΛΕΙΟΥ
Keyword(s):  
Expert Systems ◽  
Test Plan ◽  
Plan Generation ◽  
Test Plan Generation

scholarly journals A Modified Approach to Test Plan Generation for Combinational Logic Blocks

VLSI Design ◽  
1996 ◽  
Vol 4 (3) ◽  
pp. 243-256
Author(s):  
Anupam Basu ◽  
Dilip K. Banerji ◽  
Amit Basu ◽  
T. C. Wilson ◽  
Jay C. Majithia
Keyword(s):  
Vlsi Circuits ◽  
Testing Time ◽  
Combinational Logic ◽  
Test Plan ◽  
Crucial Step ◽  
Plan Generation ◽  
Test Methodology ◽  
Test Plan Generation ◽  
Total Testing Time ◽  
Logic Blocks

Generation of test plans is a crucial step for testing VLSI circuits. This paper presents a modified approach to test plan generation for the BILBO test methodology. A few limitations of the existing approaches have been identified and methods to address these have been suggested. The proposed approach has been implemented for the general case of n-port combinational logic blocks (CLBs). However, due to limitations of space and for clarity, only 2-port CLBs are considered in this paper. For this case, the problem is modelled as a Step Scheduling Matrix and an algorithm is presented for the solution. The algorithm has been tested on a number of benchmark circuits and the results are compared with those obtained through existing methods. The effectiveness of the proposed approach is clear from the results, as it contributes to the reduction in total testing time as well as generates a larger number of test plans.

scholarly journals Weibull Analysis Techniques on a Desktop Computer

1988 ◽  
Author(s):  
J. L. Byers
Keyword(s):  
Data File ◽  
Desktop Computer ◽  
Plan Generation ◽  
Central Computer ◽  
Desktop Computers ◽  
Computer Codes ◽  
Direct Input ◽  
Naval Air Systems Command ◽  
Analytical Tools ◽  
Test Plan Generation

This paper presents a summary of a task to provide individual Navy project engineers with analytical tools that enable them to perform Weibull failure and related analyses on a desktop computer. Similar tools have been available on mainframe computers for over a decade while only fragmented and incomplete tools existed for desktop computers. There is now available an integrated computer program that allows Navy project engineers and other Navy analysts to perform rigorous trade-off and what-if analyses in an interactive manner without having to send the problem off to their organizational central computer facility. The resulting computer codes exist in several forms to fit the various needs and computer configurations, such as: direct input of data, data file creation and update, and non-printing versions for those who have no printer available. Included in the codes are three Monte Carlo routines and several test plan generation codes. These codes have not been released to the general public as yet and are currently restricted to Navy units such as laboratories, Naval Aircraft Rework Facilities (NARF) and the Naval Air Systems Command Headquarters (NAVAIR). Public release is expected in mid-FY 89.

Sign in / Sign up

Export Citation Format

Share Document