A 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through Silicon Via and Hybrid Cu-Adhesive Bonding

2011 ◽  
pp. 263-295
Author(s):  
Fei Liu
Keyword(s):  
Adhesive Bonding ◽  
Three Dimensional ◽  
Integration Scheme ◽  
Wafer Level ◽  
Through Silicon Via

Damascene-Patterned Metal-Adhesive (Cu-BCB) Redistribution Layers

2006 ◽  
Vol 970 ◽  
Author(s):  
Ronald J. Gutmann ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu
Keyword(s):  
Bonding Strength ◽  
Adhesive Bonding ◽  
Process Integration ◽  
Three Dimensional ◽  
Adhesive Layer ◽  
Wafer Level ◽  
Technology Platform ◽  
Metal Bonding ◽  
Wafer Level Packaging ◽  
Metal Metal

ABSTRACTA monolithic, wafer-level three-dimensional (3D) technology platform is described that is compatible with next-generation wafer level packaging (WLP) processes. The platform combines the advantages of both (1) high bonding strength and adaptability to IC wafer topography variations with spin-on dielectric adhesive bonding and (2) process integration and via-area advantages of metal-metal bonding. A copper-benzocyclobutene (Cu-BCB) process is described that incorporates single-level damascene-patterned Cu vias with partially-cured BCB as the bonding adhesive layer. A demonstration vehicle consisting of a two-wafer stack of 2-4 μm diameter vias has shown the bondability of both Cu-to-Cu and BCB-to-BCB. Planarization conditions to achieve BCB-BCB bonding with low-resistance Cu-Cu contacts have been examined, with wafer-scale planarization requirements compared to other 3D platforms. Concerns about stress induced at the tantalum (Ta) liner-to-BCB interface resulting in partial delamination are discussed. While across-wafer uniformity has not been demonstrated, the viability of this WLP-compatible 3D platform has been shown.

scholarly journals Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1586
Author(s):  
Zhong Fang ◽  
Peng You ◽  
Yijie Jia ◽  
Xuchao Pan ◽  
Yunlei Shi ◽  
...  
Keyword(s):  
Adhesive Bonding ◽  
Low Cost ◽  
Three Dimensional ◽  
System Level ◽  
Process Conditions ◽  
Wafer Level ◽  
3D Integration ◽  
Bonding Pressure ◽  
Curing Conditions ◽  
Integration Technology

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

SiPs in the medical domain and in the defense and industrial domain produced with WDoDTM technology

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000143-000181
Author(s):  
Pascal COUDERC ◽  
Jérôme NOIRAY
Keyword(s):  
High Performance ◽  
Process Integration ◽  
New Technology ◽  
Three Dimensional ◽  
Integrated System ◽  
Electrical Performance ◽  
Integration Scheme ◽  
Disruptive Technology ◽  
Wafer Level ◽  
Wafer Processing

Based on Wire free Die on Die disruptive technology (WDoDTM), complex SiPs can be manufactured in a small factor package size. Stacking known good rebuilt wafers allows high yields while integrating high performance devices (1). Wafer processing is done with e-WLB technology and a specific redistribution layer (RDL) is designed to match with 3D PLUS bus metal edge interconnect technology. 300 mm rebuilt wafers are processed and thinned down to 200 μm before stacking and polymer bonding. Bonding alignment is within ±5 μm allowing small lateral pitches demonstrating WDoDTM versatility with denser IO products such as FPGA. Besides, this new process integration scheme allows the stacking of both conventional boards with SMDs not available at wafer level together with rebuilt wafers made of known good dies. WDoDTM technology has been successfully used with different kind of products in the defense and medical markets. A calculator node including a 484 I/O FPGA with 2 mDDR and an EEPROM in addition to more than 150 decoupling capacitors was manufactured and is exhibiting better electrical performance when compared to the 2 dimensions version. Moreover, a medical implant has been successfully developed embedding 2 ASICS and several PICS capacitors allowing an 8 times shrink of the electronics compared to advance lead based pacemakers.. With this new technology, 3D PLUS is highlighting the way to highly integrated System in Package (SiP) and demonstrates its know-how in the three dimensional integration.

A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application

2012 ◽  
Vol 12 (2) ◽  
pp. 209-216 ◽  
Author(s):  
Cheng-Ta Ko ◽  
Zhi-Cheng Hsiao ◽  
Yao-Jen Chang ◽  
Peng-Shu Chen ◽  
Yu-Jiau Hwang ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Integration Scheme ◽  
Wafer Level

Enhancement of through Silicon via Sidewall Quality by Nanosecond Laser Pulses with Chemical Etching Process

2012 ◽  
Vol 579 ◽  
pp. 3-9 ◽  
Author(s):  
Chao Wei Tang ◽  
Shih Chieh Tseng ◽  
Hong Tsu Young ◽  
Kuan Ming Li ◽  
Mike Yang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Chemical Etching ◽  
Three Dimensional ◽  
Laser Pulses ◽  
Nanosecond Laser ◽  
Wafer Level ◽  
Sidewall Roughness ◽  
Through Silicon Via ◽  
Three Dimensional Integrated Circuit ◽  
Micrometer Scale

Through-silicon via (TSV) is an emerging technology for three-dimensional integrated circuit, system in package, and wafer level packaging applications. In this study, a wet chemical etching (WCE) process has been employed to enhance the sidewall quality of TSVs fabricated using nanosecond (ns) laser pulses. Experimental results show that the TSV sidewall roughness can be markedly reduced, from micrometer scale to nanometer scale. We concluded that the proposed method would enable semiconductor manufactures to use ns laser drilling for industrial TSV fabrication as the desired TSV sidewall quality can be achieved by incorporating the WCE process, which is suitable for mass production.

scholarly journals Three-Dimensional Elastodynamic Analysis Employing Partially Discontinuous Boundary Elements

Algorithms ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 129
Author(s):  
Yuan Li ◽  
Ni Zhang ◽  
Yuejiao Gong ◽  
Wentao Mao ◽  
Shiguang Zhang
Keyword(s):  
Side Effect ◽  
Domain Boundary ◽  
Three Dimensional ◽  
Boundary Integral ◽  
Integration Scheme ◽  
Computational Accuracy ◽  
Time Step ◽  
Corner Points ◽  
Discontinuous Elements ◽  
The Time Domain

Compared with continuous elements, discontinuous elements advance in processing the discontinuity of physical variables at corner points and discretized models with complex boundaries. However, the computational accuracy of discontinuous elements is sensitive to the positions of element nodes. To reduce the side effect of the node position on the results, this paper proposes employing partially discontinuous elements to compute the time-domain boundary integral equation of 3D elastodynamics. Using the partially discontinuous element, the nodes located at the corner points will be shrunk into the element, whereas the nodes at the non-corner points remain unchanged. As such, a discrete model that is continuous on surfaces and discontinuous between adjacent surfaces can be generated. First, we present a numerical integration scheme of the partially discontinuous element. For the singular integral, an improved element subdivision method is proposed to reduce the side effect of the time step on the integral accuracy. Then, the effectiveness of the proposed method is verified by two numerical examples. Meanwhile, we study the influence of the positions of the nodes on the stability and accuracy of the computation results by cases. Finally, the recommended value range of the inward shrink ratio of the element nodes is provided.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

scholarly journals Computation of Three-Dimensional, Rotational Flow Through Turbomachinery Blade Rows for Improved Aerodynamic Design Studies

1986 ◽  
Author(s):  
S. V. Subramanian ◽  
R. Bozzola ◽  
Louis A. Povinelli
Keyword(s):  
Three Dimensional ◽  
Maximum Flow ◽  
Cost Effective ◽  
Computer Code ◽  
Integration Scheme ◽  
Aerodynamic Design ◽  
Design Studies ◽  
Flow Equations ◽  
Transonic Compressor ◽  
Numerical Predictions

The performance of a three dimensional computer code developed for predicting the flowfield in stationary and rotating turbomachinery blade rows is described in this study. The four stage Runge-Kutta numerical integration scheme is used for solving the governing flow equations and yields solution to the full, three dimensional, unsteady Euler equations in cylindrical coordinates. This method is fully explicit and uses the finite volume, time marching procedure. In order to demonstrate the accuracy and efficiency of the code, steady solutions were obtained for several cascade geometries under widely varying flow conditions. Computed flowfield results are presented for a fully subsonic turbine stator and a low aspect ratio, transonic compressor rotor blade under maximum flow and peak efficiency design conditions. Comparisons with Laser Anemometer measurements and other numerical predictions are also provided to illustrate that the present method predicts important flow features with good accuracy and can be used for cost effective aerodynamic design studies.

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