Study on the Charge Collection Mechanism of Single Event Transient Effect for Nano N-Channel Metal Oxide Semiconductor Field Effect Transistor

2020 ◽  
Vol 15 (5) ◽  
pp. 637-644
Author(s):  
Minru Hao ◽  
Chenguang Liao ◽  
Qian Zhang ◽  
Yan Zhang ◽  
Min Shao ◽  
...  
Keyword(s):  
Electric Field ◽  
Integrated Circuit ◽  
Depletion Region ◽  
Transient Current ◽  
Oxide Semiconductor ◽  
Charge Collection ◽  
Gate Length ◽  
Single Event ◽  
Drain Bias ◽  
Peak Value

Based on the mechanism of charge collection, drift and diffusion, the influence of incident position, drain bias and incident particle LET (Linear Energy Transfer) value on the charge collection of NMOS devices is analyzed. It is found that the strongest electric field in drain depletion region is at 70 nm, and the maximum transient current is 3.43 mA. Drain bias affects the electric field in drain region. The higher drain bias is, the greater the electric field is, and the transient current is the larger of the peak value is, and the change of drain bias does not affect the diffusion current part; the larger the LET is, the larger the set current is, and the transient current peak value and collection charge increase linearly with the increase of LET. In addition, for a single transistor, the influence of the reduction of gate length on the bipolar amplification is analyzed, which is discovered that the reduction of gate length results in the aggravation of the single event effect. Therefore, the simulation results provide valuable reference for research on irradiation reliability and application of strained integrated circuit of Si Nano-scale NMOSFET.

Particle Monte Carlo modeling of single-event transient current and charge collection in integrated circuits

2014 ◽  
Vol 54 (9-10) ◽  
pp. 2278-2283 ◽  
Author(s):  
J.L. Autran ◽  
M. Glorieux ◽  
D. Munteanu ◽  
S. Clerc ◽  
G. Gasiot ◽  
...  
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Transient Current ◽  
Charge Collection ◽  
Single Event ◽  
Single Event Transient ◽  
Monte Carlo Modeling

scholarly journals Mechanisms of Heavy Ion-Induced Single Event Burnout in 4H-SiC Power MOSFETs

2020 ◽  
Vol 1004 ◽  
pp. 889-896
Author(s):  
Joseph McPherson ◽  
Collin W. Hitchcock ◽  
T. Paul Chow ◽  
Wei Ji ◽  
Andrew Woodworth
Keyword(s):  
Electric Field ◽  
Field Effect ◽  
Impact Ionization ◽  
Field Effect Transistors ◽  
Heavy Ion ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Single Event ◽  
Power Mosfets ◽  
Single Event Effect

This paper describes the mechanisms behind the failure of silicon carbide (SiC) Power MOSFETs (metal oxide semiconductor field effect transistors) when struck by a heavy ion. The modeled device is designed to simulate a commercially available 1200 V power MOSFET under the strike of a silver ion with a Linear Energy Transfer (LET) of 46 MeV-cm2/mg commonly used in single event effect (SEE) testing. The device is shown in simulation to fail near 500 V, which is in close agreement to experiments. The failure occurs near the interface between the epitaxial layer and the substrate layer due to the rapid increase of the electric field in that region and destruction of the device from impact ionization. Two improved designs were proposed and investigated that would help to mitigate the electric field in these regions and improve the device’s tolerance to single-event burnout (SEB). The new designs increased the voltage at which SEB occurs from 500 V to over 900 V and increased the specific on-resistance (Ron,sp) by only 5%.

scholarly journals Simulation Study of Silicon-Based Single-Photon Avalanche Diodes with Double Buried Layers and Deep Trench Electrodes

Crystals ◽  
2021 ◽  
Vol 11 (10) ◽  
pp. 1176
Author(s):  
Yanyan Du ◽  
Bo Li ◽  
Xu Wang
Keyword(s):  
Electric Field ◽  
Near Infrared ◽  
Single Photon ◽  
Depletion Region ◽  
Simulation Software ◽  
Oxide Semiconductor ◽  
Infrared Band ◽  
Deep Trench ◽  
Buried Layers ◽  
Silicon Based

In this paper we present a study of a silicon-based Single-Photon Avalanche Diode (SPAD) in the near-infrared band with double buried layers and deep trench electrodes fabricated by the complimentary metal–oxide semiconductor (CMOS) technology. The deep trench electrodes aim to promote the movement of carriers in the device and reduce the transit time of the photo-generated carrier. The double buried layers are introduced to increase the electric field in the avalanche area and withstand a larger excess bias voltage as its larger depletion region. The semiconductor device simulation software TCAD is used to simulate the performance of this SPAD model, such as the I-V characteristic, the electric field and the Photon Detection Efficiency (PDE). Further optimization of the structure are studied with influence factors such as the doping concentration and depletion region thickness. Based on the results in this study, the designed a structure that can provide a high detecting efficiency in the near-infrared band.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Gate-Length and Drain-Bias Dependence of Band-to-Band Tunneling-Induced Drain Leakage in Irradiated Fully Depleted SOI Devices

2008 ◽  
Vol 55 (6) ◽  
pp. 3259-3264 ◽  
Author(s):  
Farah E. Mamouni ◽  
Sriram K. Dixit ◽  
Ronald D. Schrimpf ◽  
Philippe C. Adell ◽  
Ivan S. Esqueda ◽  
...  
Keyword(s):  
Gate Length ◽  
Fully Depleted ◽  
Band To Band Tunneling ◽  
Drain Bias ◽  
Soi Devices
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