Two-Dimensional Analytical Modeling of Fully Depleted Short-Channel DG SOI MOSFET

2009 ◽  
Author(s):  
Seyed Ebrahim Hosseini ◽  
Mohammad Kazem Anvarifard ◽  
Mahdi Gordi Armaki
Keyword(s):  
Analytical Modeling ◽  
Two Dimensional ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet

Modeling of Sub Threshold Current and Sub Threshold Swing of Short-Channel Fully-Depleted SOI MOSFET with Back-Gate Control

2017 ◽  
Vol 9 (01) ◽  
pp. 67-72
Author(s):  
Sarvesh Dubey ◽  
Rahul Mishra
Keyword(s):  
Analytical Modeling ◽  
Threshold Current ◽  
Short Channel Effects ◽  
Short Channel ◽  
Simulation Data ◽  
Back Gate ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Effects ◽  
Gate Control

The present paper deals with the analytical modeling of subthreshold characteristics of short-channel fully-depleted recessed-source/drain SOI MOSFET with back-gate control. The variations in the subthreshold current and subthreshold swing have been analyzed against the back-gate bias voltage, buried-oxide (BOX) thickness and recessed source/drain thickness to assess the severity of short-channel effects in the device. The model results are validated by simulation data obtained from two-dimensional device simulator ATLAS from Silvaco.

scholarly journals Analytical Modeling and Simulation of Nanoscale Fully Depleted Dual Metal Gate SOI MOSFET

2019 ◽  
Vol 8 (10) ◽  
pp. 2946-2950
Keyword(s):  
Analytical Modeling ◽  
Cmos Technology ◽  
Step Function ◽  
Device Structure ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
New Device ◽  
Dual Metal ◽  
Dual Material

The demand and development of scaled semiconductors devices for upcoming challenges in VLSI technology is unending. CMOS technology plays a very important role in fulfilling this criterion. The conventional MOSFET exhibits short channel effects (SCE) and performance degradation when scaled down in the nanometer regime. In order to meet the required enhanced performance and to further increase the device density new materials and new device structures have been developed. This paper analyses the performance characteristics of one of such improved device structure i.e Fully Depleted Silicon over Insulator (FDSOI) which also incorporate the gate having two metals of different work function specifically called Dual Material Gate (DMG) SOI MOSFET. The analytical modeling for this device structure has also been carried out. The simulation characteristics match closely with analytical results and as the surface potential profile of the device has step function in ensures that this device effectively reduces the SCE.

scholarly journals 2-D analytical modeling of dual material gate fully depleted SOI MOSFET with high-k dielectric

2008 ◽  
Vol 57 (6) ◽  
pp. 3807
Author(s):  
Luan Su-Zhen ◽  
Liu Hong-Xia ◽  
Jia Ren-Xu ◽  
Cai Nai-Qiong
Keyword(s):  
Analytical Modeling ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
High K ◽  
High K Dielectric ◽  
Dual Material

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Two-Dimensional Analytical Modeling of the Source/Drain Engineering Influence on Short-Channel Effects in SOI MOSFET's

1995 ◽  
Vol 34 (Part 1, No. 2B) ◽  
pp. 822-826 ◽  
Author(s):  
Hans-Oliver Joachim ◽  
Yasuo Yamaguchi ◽  
Yasuo Inoue ◽  
Natsuro Tsubouchi
Keyword(s):  
Analytical Modeling ◽  
Two Dimensional ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects
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