scholarly journals Effect of Coercive Voltage and Charge Injection on Performance of a Ferroelectric-Gate Thin-Film Transistor

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
P. T. Tue ◽  
T. Miyasako ◽  
E. Tokumitsu ◽  
T. Shimoda
Keyword(s):  
Thin Film ◽  
Indium Tin Oxide ◽  
Thin Film Transistor ◽  
Charge Injection ◽  
Memory Window ◽  
Gate Insulator ◽  
Insulator Layer ◽  
Capping Layer ◽  
Insulator Layers ◽  
Injection Effect

We adopted a lanthanum oxide capping layer between semiconducting channel and insulator layers for fabrication of a ferroelectric-gate thin-film transistor memory (FGT) which uses solution-processed indium-tin-oxide (ITO) and lead-zirconium-titanate (PZT) film as a channel layer and a gate insulator, respectively. Good transistor characteristics such as a high “on/off” current ratio, high channel mobility, and a large memory window of 108, 15.0 cm2 V−1 s−1, and 3.5 V were obtained, respectively. Further, a correlation between effective coercive voltage, charge injection effect, and FGT’s memory window was investigated. It is found that the charge injection from the channel to the insulator layer, which occurs at a high electric field, dramatically influences the memory window. The memory window’s enhancement can be explained by a dual effect of the capping layer: (1) a reduction of the charge injection and (2) an increase of effective coercive voltage dropped on the insulator.

ITO-Channel Ferroelectric-Gate Thin Film Transistor with Large On/off Current Ratio

2007 ◽  
Vol 997 ◽  
Author(s):  
Eisuke Tokumitsu ◽  
Masaru Senoo ◽  
Etsu Shin ◽  
Tomofumi Fujimura
Keyword(s):  
Thin Film ◽  
Indium Tin Oxide ◽  
Thin Film Transistor ◽  
Sol Gel ◽  
Mechanical Polishing ◽  
Gate Insulator ◽  
Polishing Process ◽  
Current Ratio ◽  
Subthreshold Voltage ◽  
Voltage Swing

AbstractIndium tin oxide (ITO)-channel ferroelectric-gate thin film transistor (TFT) with large on/off current ratio is demonstrated by using mechanical polishing process to planarize the surface of ferroelectric bottom gate insulator (Bi,La)4Ti3O12 (BLT). It is shown that the mechanical polishing of the sol-gel derived polycrystalline ferroelectric BLT films causes no degradation in electrical properties. ITO channel layer was then deposited on the planarized BLT gate insulator to fabricate ferroelectric-gate TFTs. The off-current of the ITO/BLT TFT fabricated with the polishing process is drastically reduced to around 10−12 A, which is four orders of magnitude lower than that of the TFT fabricated without the polishing process. The obtained on/off current ratio is more than 107. In addition, a subthreshold voltage swing as small as 200 mV/decade was obtained.

Lanthanum Oxide Capping Layer for Solution-Processed Ferroelectric-Gate Thin-Film Transistors

2011 ◽  
Vol 1337 ◽  
Author(s):  
Tue T. Phan ◽  
Trinh N. Q. Bui ◽  
Takaaki Miyasako ◽  
Thanh V. Pham ◽  
Eisuke Tokumitsu ◽  
...  
Keyword(s):  
Thin Film ◽  
Indium Tin Oxide ◽  
Thin Film Transistors ◽  
Gate Insulator ◽  
Data Retention ◽  
Solution Processed ◽  
Capping Layer ◽  
Large Memory ◽  
Ferroelectric Memories ◽  
Atomically Flat

ABSTRACTWe report on the use of La2O3 (LO) as a capping layer for ferroelectric-gate thin-film transistors (FGTs) with solution-processed indium-tin-oxide (ITO) channel and Pb(Zr,Ti)O3 (PZT) gate insulator. The fabricated FGT exhibited excellent performance with a high “ON/OFF” current ratio (ION/IOFF) and a large memory window (∆Vth) of about 108 and 3.5 V, respectively. Additionally, a significantly improved data retention time (more than 16 hours) as compared to the ITO/PZT structure was also obtained as a result of good interface properties between the ITO channel and LO/PZT stacked gate insulator. We suggest that the LO capping layer acts as a barrier to prevent the interdiffusion and provides atomically flat ITO/LO/PZT interface. This all-oxide FGT device is very promising for future ferroelectric memories.

Determination of the Defect Redistribution and Charge Injection Contributions to the a-Si:H Thin-Film Transistor Instability

1994 ◽  
Vol 336 ◽  
Author(s):  
R. Carluccio ◽  
A. Pecora ◽  
D. Massimiani ◽  
G. Fortunato
Keyword(s):  
Thin Film ◽  
Silicon Dioxide ◽  
Field Effect ◽  
Thin Film Transistor ◽  
High Stress ◽  
Charge Injection ◽  
Gate Insulator ◽  
Parasitic Resistance ◽  
Moderate Stress

ABSTRACTThe effects of bias-stressing n- and p-channel thin-film transistors, employing thermal silicon dioxide as gate insulator, have been analysed by using different techniques, including field-effect, space-charge photomodulation and photo-induced discharge. Photo-induced discharge experiments have pointed out as parasitic resistance effects can be present in p-channel devices. In order to reduce this problem, thin active layer p-channel devices have been fabricated and, combining these results to those relative to the n-channel transistors, we deduced a predominance of charge injection at low and moderate stress-biases while at high-stress biases modifications in the density of states take place.

Study of Transport Through Low-Temperature GaAs Surface Insulator Layers

1991 ◽  
Vol 241 ◽  
Author(s):  
J. P. Ibbetson ◽  
L.-W. Yin ◽  
M. Hashemi ◽  
A. C. Gossard ◽  
U. K. Mishra
Keyword(s):  
Material Properties ◽  
Surface Effect ◽  
Thin Layers ◽  
Gate Insulator ◽  
High Resistivity ◽  
Growth Surface ◽  
Insulator Layer ◽  
Insulator Layers ◽  
Low Temperature Gaas ◽  
Effective Buffer

ABSTRACTSince epilayers of GaAs grown at low substrate temperature (LTGaAs) and annealed at 600°C were first demonstrated to be an effective buffer layer for eliminating backgating effects, the material properties and electronic characteristics of bulk LTGaAs have been actively investigated. Less attention has been paid to thin layers of LTGaAs (∼2000Å), although these have been shown to improve gate-to-drain breakdown characteristics when incorporated as the surface insulator layer in GaAs MISFET's. In bulk LTGaAs that has been annealed for 10 minutes at 600°C, the formation of arsenic precipitates with a density of 1018 cm-3 has been observed. These are considered to be at least partially responsible for the high resistivity of LTGaAs2. While the exact mechanism of precipitate formation is currently unknown, it would seem reasonable to expect the availability of the growth surface to have a significant effect on any defect redistribution during the anneal. This surface effect would become increasingly apparent as the LTGaAs layer thickness was decreased. It is desirable for MISFET applications that the LTGaAs gate insulator layer be as thin as possible, whilst maintaining high breakdown, in order to maximize device transconductance. To achieve this, it is important to understand how the observed bulk features (such as ∼60Å size arsenic precipitates) are affected in thin LTGaAs layers

Mobility improvement of LTPS thin film transistor using stacked capping layer

2021 ◽  
pp. 111591
Author(s):  
Taeyong Kim ◽  
Donggi Shin ◽  
Jinsu Park ◽  
Duy Phong Pham ◽  
Junsin Yi
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Capping Layer

scholarly journals Demonstration on Ferroelectric-gate Thin Film Transistor NAND-type Array with Disturbance-free Operation

2019 ◽  
Vol 35 (2) ◽  
Author(s):  
Bui Nguyen Quoc Trinh
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Sol Gel ◽  
Gate Insulator ◽  
Current Ratio ◽  
Memory State ◽  
Small Loss ◽  
Memory Circuit ◽  
Novel Concept ◽  
Data Reading

Abstract: A novel concept of NAND memory array has been proposed by using only ferroelectric-gate thin film transistors (FGTs), whose structure is constructed from a sol-gel ITO channel and a sol-gel stacked ferroelectric between Bi3.25La0.75Ti3O12 and PbZr0.52TiO0.48O3 (BLT/PZT) gate insulator. Interestingly, ferroelectric cells with a wide memory window of 3 V and a large on/off current ratio of 6 orders, have been successfully integrated in a NAND memory circuit. To protect data writing or reading from disturbance, ferroelectric transistor cells are directly used, instead of paraelectric transistor cells as usual. As a result, we have verified disturbance-free operation for data reading and writing, with a small loss of the memory state and a low power consumption, in principle. Keywords: ITO, PZT, NAND, FeRAM, ferroelectric.

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