scholarly journals Shedding Physical Synthesis Area Bloat

VLSI Design ◽  
2011 ◽  
Vol 2011 ◽  
pp. 1-10 ◽  
Author(s):  
Ying Zhou ◽  
Charles J. Alpert ◽  
Zhuo Li ◽  
Cliff Sze ◽  
Louise H. Trevillyan
Keyword(s):  
Power Dissipation ◽  
Design Flow ◽  
Low Power Consumption ◽  
Gate Sizing ◽  
Buffer Insertion ◽  
Growth Reduction ◽  
Timing Closure ◽  
Area Reduction ◽  
Area Increase ◽  
Physical Synthesis

Area bloat in physical synthesis not only increases power dissipation, but also creates congestion problems, forces designers to enlarge the die area, rerun the whole design flow, and postpone the design deadline. As a result, it is vital for physical synthesis tools to achieve timing closure and low power consumption with intelligent area control. The major sources of area increase in a typical physical synthesis flow are from buffer insertion and gate sizing, both of which have been discussed extensively in the last two decades, where the main focus is individual optimized algorithm. However, building a practical physical synthesis flow with buffering and gate sizing to achieve the best timing/area/runtime is rarely discussed in any previous literatures. In this paper, we present two simple yet efficient buffering and gate sizing techniques and achieve a physical synthesis flow with much smaller area bloat. Compared to a traditional timing-driven flow, our work achieves 12% logic area growth reduction, 5.8% total area reduction, 10.1% wirelength reduction, and 770 ps worst slack improvement on average on 20 industrial designs in 65 nm and 45 nm.

scholarly journals Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage Assignment

Technologies ◽  
2021 ◽  
Vol 9 (4) ◽  
pp. 92
Author(s):  
Dimitrios Mangiras ◽  
Giorgos Dimitrakopoulos
Keyword(s):  
Lagrangian Relaxation ◽  
Threshold Voltage ◽  
Operating Conditions ◽  
Design Flow ◽  
Gate Sizing ◽  
Timing Closure ◽  
Last Mile ◽  
Placement And Routing ◽  
Routing Congestion ◽  
Timing Violations

Timing closure remains one of the most critical challenges of a physical synthesis flow, especially when the design operates under multiple operating conditions. Even if timing is almost closed at the end of the flow, last-mile placement and routing congestion optimizations may introduce new timing violations. Correcting such violations needs minimally disruptive techniques such as threshold voltage reassignment and gate sizing that affect only marginally the placement and routing of the almost finalized design. To this end, we transform a powerful Lagrangian-relaxation-based optimizer, used for global timing optimization early in the design flow, into a practical incremental timing optimizer that corrects small timing violations with fast runtime and without increasing the area/power of the design. The proposed approach was applied to already optimized designs of the ISPD 2013 benchmarks assuming that they experience new timing violations due to local wire rerouting. Experimental results show that in single corner designs, timing is improved by more than 36% on average, using 45% less runtime. Correspondingly, in a multicorner context, timing is improved by 39% when compared to the fully-fledged version of the timing optimizer.

Efficient timing closure with a transistor level design flow

2007 ◽  
Author(s):  
Cristiano Lazzari ◽  
Cristiano Santos ◽  
Adriel Ziesemer ◽  
Lorena Anghel ◽  
Ricardo Reist
Keyword(s):  
Design Flow ◽  
Timing Closure ◽  
Level Design

DYNAMIC POWER DISSIPATION FORMULATION FOR APPLICATION IN DYNAMIC PROGRAMMING BUFFER INSERTION ALGORITHM

2016 ◽  
Vol 78 (11) ◽  
Author(s):  
Chessda Uttraphan ◽  
Nasir Shaikh-Husin ◽  
M. Khalil-Hani
Keyword(s):  
Dynamic Programming ◽  
Closed Form ◽  
Power Dissipation ◽  
Closed Form Solution ◽  
Propagation Delay ◽  
Form Solution ◽  
Buffer Insertion ◽  
Dynamic Power ◽  
Insertion Algorithm ◽  
Series Of Experiments

Buffer insertion is a very effective technique to reduce propagation delay in nano-metre VLSI interconnects. There are two techniques for buffer insertion which are: (1) closed-form solution and (2) dynamic programming. Buffer insertion algorithm using dynamic programming is more useful than the closed-form solution as it allows the use of multiple buffer types and it can be used in tree structured interconnects. As design dimension shrinks, more buffers are needed to improve timing performance. However, the buffer itself consumes power and it has been shown that power dissipation of buffers is significant. Although there are many buffer insertion algorithms that were able to optimize propagation delay with power constraint, most of them used the closed-form solution. Hence, in this paper, we present a formulation to compute dynamic power dissipation of buffers for application in dynamic programming buffer insertion algorithm. The proposed formulation allows dynamic power dissipation of buffers to be computed incrementally. The technique is validated by comparing the formulation with the standard closed-form dynamic power equation. The advantage of the proposed formulation is demonstrated through a series of experiments where it is applied in van Ginneken’s algorithm. The results show that the output of the proposed formulation is consistent with the standard closed-form formulation. Furthermore, it also suggests that the proposed formulation is able to compute dynamic power dissipation for buffer insertion algorithm with multiple buffer types.  

A Kind of Design for Intelligent Photoelectric Tracing Trolley

2013 ◽  
Vol 300-301 ◽  
pp. 1600-1603
Author(s):  
Wei Gao
Keyword(s):  
Intelligent Control ◽  
Software Design ◽  
High Reliability ◽  
Design Flow ◽  
Low Power Consumption ◽  
Infrared Sensor ◽  
Simple Circuit ◽  
Intelligent Control System ◽  
Circuit Structure ◽  
High Intelligence

The intelligent control system of electric tracking trolley that uses infrared sensor as sensitive component and AT89S51 microcontroller as control core is designed in this paper. The design employees infrared receiver and transmitter to detect the runway information and AT89S51 to control the electric trolley tracking and auto parking. The system has the characters of simple circuit structure, high reliability, high intelligence and low power consumption. The paper describes the system's hardware and software design flow in detail. The result shows that the smart trolley in the absence of human intervention could independently run and stably track the target.

A design flow for physical synthesis of digital cells with ASTRAN

2014 ◽  
Author(s):  
Adriel Ziesemer ◽  
Ricardo Reis ◽  
Matheus T. Moreira ◽  
Michel E. Arendt ◽  
Ney L.V. Calazans
Keyword(s):  
Design Flow ◽  
Physical Synthesis
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