scholarly journals Non-Equilibrium Hole Transport in Deep Sub-Micron Well-Tempered Si p-MOSFETs

VLSI Design ◽  
2001 ◽  
Vol 13 (1-4) ◽  
pp. 169-173
Author(s):  
J. R. Watling ◽  
Y. P. Zhao ◽  
A. Asenov ◽  
J. R. Barker

As MOSFETs are scaled to deep submicron dimensions non-equilibrium, near ballistic, transport in p-MOSFETs becomes important. Recent experimental data indicates that as MOSFETs are scaled the performance gap between n and p-channel shrinks. Nonequilibrium transport effects and performance potentials of ‘Well Tempered’ Si p- MOSFETs with gate lengths of 50 and 25 nm are studied. Monte Carlo and calibrated Drift Diffusion simulations of these devices provide a quantitative estimate of the importance and the influence of non-equilibrium transport on submicron device performance. A possible explanation for the closing performance gap between n- and p-channel MOSFETs is offered.

2020 ◽  
Vol 8 (1) ◽  
Author(s):  
Jason Myers ◽  
Joe Bhaseen ◽  
Rosemary J. Harris ◽  
Benjamin Doyon

We propose exact results for the full counting statistics, or the scaled cumulant generating function, pertaining to the transfer of arbitrary conserved quantities across an interface in homogeneous integrable models out of equilibrium. We do this by combining insights from generalised hydrodynamics with a theory of large deviations in ballistic transport. The results are applicable to a wide variety of physical systems, including the Lieb-Liniger gas and the Heisenberg chain. We confirm the predictions in non-equilibrium steady states obtained by the partitioning protocol, by comparing with Monte Carlo simulations of this protocol in the classical hard rod gas. We verify numerically that the exact results obey the correct non-equilibrium fluctuation relations with the appropriate initial conditions.


2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Lars Haffke

Purpose Money Laundering Reporting Officers (MLROs) carry out day-to-day anti-money laundering (AML) tasks while directors ultimately remain responsible for AML compliance. Therefore, directors’ expectations of what their MLROs do should ideally coincide with what their actual tasks to minimise liability risk. This paper aims to test for gaps between MLROs and their directors in terms of knowledge, expectations and performance of AML tasks. Likewise, it is researched whether MLROs and directors communicate well with regard to MLROs’ tasks. Design/methodology/approach This paper first develops a model for analysing the dyadic relationship between MLROs and their directors, based on the audit expectation-performance gap. Second, a paired electronic survey of MLROs and directors of German companies was conducted in autumn 2020, testing for participants’ knowledge, expectations and performance of possible AML tasks (n = 136 pairs). Findings While there is no knowledge or performance gap among MLROs and directors, expectations among them are partially unreasonable and their communication needs to be improved. Additionally, this study suggests that MLROs of German non-financial businesses are less knowledgeable, perform AML duties more poorly, and communicate less effectively with their directors. Practical implications Training of MLROs and communication with their directors need to be improved. Especially in the non-financial sector, action is urgently required. Originality/value This paper reports the results of the first paired survey of MLROs and their directors, offering unique insights into their relationship and the status of private AML efforts.


Author(s):  
Raj Kumar ◽  
Shashi Bala ◽  
Arvind Kumar

To have enhanced drive current and diminish short channel effects, planer MOS transistors have migrated from single-gate devices to three-dimensional multi-gate MOSFETs. The gate-all-around nanowire field-effect transistor (GAA NWFET) and nanotube or double gate-all-around field-effect transistors (DGGA-NTFET) have been proposed to deal with short channel effects and performance relates issues. Nanowire and nanotube-based field-effect transistors can be considered as leading candidates for nanoscale devices due to their superior electrostatic controllability, and ballistic transport properties. In this work, the performance of GAA NWFETs and DGAA-NT FETs will be analyzed and compared. III-V semiconductor materials as a channel will also be employed due to their high mobility over silicon. Performance analysis of junctionless nanowire and nanotube FETs will also be compared and presented.


2020 ◽  
Vol 2 (6) ◽  
pp. 2514-2524
Author(s):  
Sahar Alialy ◽  
Koorosh Esteki ◽  
Mauro S. Ferreira ◽  
John J. Boland ◽  
Claudia Gomes da Rocha

The nature and direction of the hysteresis in memristive devices is critical to device operation and performance and the ability to realise their potential in neuromorphic applications.


VLSI Design ◽  
1998 ◽  
Vol 8 (1-4) ◽  
pp. 253-256
Author(s):  
F. Gámiz ◽  
J. B. Roldán ◽  
J. A. López-Villanueva

Electron transport properties of strained-Si on relaxed Si1 – xGex channel MOSFETs have been studied using a Monte Carlo simulator. The steady- and non-steady-state high-longitudinal field transport regimes have been described in detail. Electronvelocity- overshoot effects are studied in deep-submicron strained-Si MOSFETs, where they show an improvement over the performance of their normal silicon counterparts. The impact of the Si layer strain on the performance enhancement are described in depth in terms of microscopic magnitudes.


2015 ◽  
Vol 3 (43) ◽  
pp. 21537-21544 ◽  
Author(s):  
Yuan Li ◽  
Nanlong Hong

As a hole transport material, PEDOT dispersed with lignosulfonate was prepared and showed promising performance in polymer solar cells.


2012 ◽  
Vol 59 (1) ◽  
pp. 206-211 ◽  
Author(s):  
Naoya Takiguchi ◽  
Shunuske Koba ◽  
Hideaki Tsuchiya ◽  
Matsuto Ogawa

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