scholarly journals Test Generators Need to be Modified to Handle CMOS Designs

VLSI Design ◽  
2001 ◽  
Vol 12 (4) ◽  
pp. 515-525
Author(s):  
Jacob Savir
Keyword(s):  
Test Generation ◽  
Cmos Technology ◽  
Test Vector ◽  
Test Set ◽  
Basic Premise ◽  
Traditional Test ◽  
Potential Test

CMOS designs have some unique properties that prevent existing test generators from computing a test vector for a fault when one might exist. The problem lies in the premises laid out on what it takes to detect a stuck-at fault. The basic premise that states that it is required to set a line to 0(1) in order to detect a stuck-at 1(0) fault, and then propagate the error to an observable point, needs to be re-examined. This is due to the existence of indeterminate states throughout the logic. The paper distinguishes between the traditional test vector (here called a hard-detect), and a potential test vector (here called a soft-detect). Our proposed test set is the union of hard and soft-detects. We also re-examine the issue of redundancy and show that it needs to be re-defined in order to comply with CMOS technology behavior.This paper shows several examples to illustrate the problem; describes what it takes in order to remedy it; proposes possible enhancements to existing test generation algorithms, and outlines the risks faced in the event that no correcting steps are taken.

scholarly journals A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation

2017 ◽  
Vol E100.D (9) ◽  
pp. 2118-2125 ◽  
Author(s):  
Toshinori HOSOKAWA ◽  
Atsushi HIRAI ◽  
Yukari YAMAUCHI ◽  
Masayuki ARAI
Keyword(s):  
Test Generation ◽  
Test Vector ◽  
Power Test

scholarly journals Testability-Driven Layout of Combinational Circuits

VLSI Design ◽  
1998 ◽  
Vol 7 (4) ◽  
pp. 347-352
Author(s):  
C. P. Ravikumar ◽  
Nikhil Sharma
Keyword(s):  
Test Generation ◽  
Test Pattern ◽  
Pattern Generator ◽  
Test Vector ◽  
Combinational Circuits ◽  
Bridging Faults ◽  
Cpu Time ◽  
On Line ◽  
Placement Algorithm ◽  
Automatic Test Pattern Generator

The layout of a circuit can influence the probability of occurrence of faults. In this paper, we develop algorithms that can take advantage of this fact to reduce the chances of hard-to-detect (HTD) faults from occurring. We primarily focus on line bridge faults in this paper. We define a bridge fault f as an HTD fault if an automatic test pattern generator fails to generate a test vector for f in a reasonable amount of CPU-time. It is common practice to drop such HTD faults from consideration during test generation. The chip fault coverage achieved by a test set is poor if the fault set consists of many HTD faults. We can combat this problem by avoiding altogether, or by reducing the probability of, the occurrence of HTD faults. In this paper, we consider hard-to-detect bridging faults and show how module placement rules can be derived to reduce the probability of these faults. A genetic placement algorithm that optimizes area while respecting these rules is presented. The placement algorithm has been implemented for standard-cell layout style on a SUN/SPARC and tested against several sample circuits.

Pseudo-Exhaustive Testing

2013 ◽  
Vol 850-851 ◽  
pp. 830-834
Author(s):  
Xin Fu ◽  
Shu Ai Fu
Keyword(s):  
Test Generation ◽  
Test Vector ◽  
Circuit Structure

There are many test generation algorithms currently. With continuously increasing of circuit scale, complexities of these algorithms are also increasingly sharply. Simple algorithms based on circuit structure, including exhaustive testing and pesudo-exhaustive testing, and simplicity of generation of test vector are more and more highlighted by scientific researchers and scholars. The dissertation mainly analyzes pseudo-exhaustive testing.

scholarly journals Automatic generation of high quality test sets via CBMC

10.29007/zbb8 ◽  
2018 ◽  
Author(s):  
Emanuele Di Rosa ◽  
Enrico Giunchiglia ◽  
Massimo Narizzano ◽  
Gabriele Palma ◽  
Alessandra Puddu
Keyword(s):  
Test Generation ◽  
Automatic Generation ◽  
Control Flow ◽  
Quality Test ◽  
High Quality ◽  
Test Set ◽  
Domain Experts ◽  
Safety Critical ◽  
Branch Coverage ◽  
Test Sets

Software Testing is the most used technique for software verification in industry. In the case of safety critical software, the test set can be required to cover a high percentage (up to 100%) of the software code according to some metrics. Unfortunately, attaining such high percentages is not easy using standard automatic tools for tests generation, and manual generation by domain experts is often necessary, thereby significantly increasing the associated costs.In previous papers, we have shown how it is possible to automatize the test generation process of C programs via the bounded model checker CBMC. In particular, we have shown how it is possible to productively use CBMC for the automatic generation of test sets covering 100% of branches of 5 modules of ERTMS/ETCS, a safety critical industrial software by Ansaldo STS. Unfortunately, the test set we automatically generated, is of lower "quality" if compared to the test set manually generated by domain experts: Both test sets attained the desired 100% branch coverage, but the sizes of the automatically generated test sets are roughly twice the sizes of the corresponding manually generated ones. Indeed, the automatically generated test sets contain redundant tests, i.e. tests that do not contribute to reach the desired 100% branch coverage. These redundant tests are useless from the perspective of the branch coverage, are not easy to detect and then to eliminate a posteriori, and, if maintained, imply additional costs during the verification process.In this paper we present a new methodology for the automatic generation of "high quality" test sets guaranteeing full branch coverage. Given an initially empty test set T, the basic idea is to extend T with a test covering as many as possible of the branches which are not covered by T. This requires an analysis of the control flow graph of the program in order to first individuate a path p with the desired property, and then the run of a tool (CBMC in our case) able to return either a test causing the execution of p or that such a test does not exist (under the given assumptions). We have experimented the methodology on 31 modules of the Ansaldo STS ERTMS/ETCS software, thus greatly extending the benchmarking set. For 27 of the 31 modules we succeeded in our goal to automatically generate "high quality" test sets attaining full branch coverage: All the feasible branches are executed by at least one test and the sizes of our test sets are significantly smaller than the sizes of the test sets manually generated by domain experts (and thus are also significantly smaller than the test sets automatically generated with our previous methodology). However, for 4 modules, we have been unable to automatically generate test sets attaining full branch coverage: These modules contain complex functions falling out of CBMC capacity.Our analysis on 31 modules greatly extends our previous analysis based on 5 modules, confirming that automatic test generation tools based on CBMC can be productively used in industry for attaining full branch coverage. Further, the methodology presented in this paper leads to a further increase in the productivity by substantially reducing the number of generated tests and thus the costs of the testing phase.

Small Test Set Generation with High Diagnosability

2016 ◽  
Vol 25 (04) ◽  
pp. 1650024 ◽  
Author(s):  
Anupam Bhar ◽  
Santanu Chattopadhyay ◽  
Indranil Sengupta ◽  
Rohit Kapur
Keyword(s):  
Fault Detection ◽  
Recent Work ◽  
Diagnostic Test ◽  
Lower Order ◽  
Fault Model ◽  
Test Vector ◽  
Test Set ◽  
Trade Off ◽  
Small Test ◽  
Test Vectors

Between fault detection and diagnostic test, there are many tests with varying degrees of diagnosability. There is trade-off between diagnosability of the test and its length. High diagnosability test is longer and takes more time. In this work, we tried to balance both by generating test slightly longer than normal detection test but with high diagnosability, without affecting fault coverage. The order of test vector application to attain more fault and diagnostic coverage in fewer test patterns is also mentioned. If more diagnosability is required, test vectors till the lower order should be used, whereas shorter test compromises on diagnosability. Our results show similar distinguishing capability as compared with a recent work but with 90% reduction in normalized time. The fault model used in this work is stuck-at fault model.

Equivalent Faults under Launch-on-Shift (LOS) Tests with Equal Primary Input Vectors

2021 ◽  
Vol 26 (4) ◽  
pp. 1-15
Author(s):  
Irith Pomeranz
Keyword(s):  
Test Generation ◽  
Fault Simulation ◽  
Single Cycle ◽  
Primary Input ◽  
Test Set ◽  
Efficient Procedure ◽  
Test Compaction ◽  
Transition Faults ◽  
Transition Fault ◽  
Types Of Faults

A recent work showed that it is possible to transform a single-cycle test for stuck-at faults into a launch-on-shift (LOS) test that is guaranteed to detect the same stuck-at faults without any logic or fault simulation. The LOS test also detects transition faults. This was used for obtaining a compact LOS test set that detects both types of faults. In the scenario where LOS tests are used for both stuck-at and transition faults, this article observes that, under certain conditions, the detection of a stuck-at fault guarantees the detection of a corresponding transition fault. This implies that the two faults are equivalent under LOS tests. Equivalence can be used for reducing the set of target faults for test generation and test compaction. The article develops this notion of equivalence under LOS tests with equal primary input vectors and provides an efficient procedure for identifying it. It presents experimental results to demonstrate that such equivalences exist in benchmark circuits, and shows an unexpected effect on a test compaction procedure.

Sign in / Sign up

Export Citation Format

Share Document