Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA

2010 ◽  
Author(s):  
Emna Amouri ◽  
Zied Marrakchi ◽  
Habib Mehrez
Keyword(s):  
Placement And Routing ◽  
Routing Techniques

scholarly journals Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle

VLSI Design ◽  
1999 ◽  
Vol 10 (1) ◽  
pp. 1-20 ◽  
Author(s):  
Dirk Stroobandt ◽  
Jan Van Campenhout
Keyword(s):  
Upper Bound ◽  
Accurate Estimate ◽  
Optimal Placement ◽  
Electronic Circuits ◽  
Length Estimation ◽  
Design Cycle ◽  
Placement And Routing ◽  
Routing Techniques ◽  
Space Requirements

Important layout properties of electronic circuits include space requirements and interconnection lengths. In the process of designing these circuits, a reliable pre-layout interconnection length estimation is essential for improving placement and routing techniques. Donath found an upper bound for the average interconnection length that follows the trends of experimentally observed average lengths. Yet, this upper bound deviates from the experimental value by a factor δ ≈ 2, which is not sufficiently accurate for some applications. We show that we obtain a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.

scholarly journals Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

2013 ◽  
Vol 2013 ◽  
pp. 1-24
Author(s):  
Emna Amouri ◽  
Habib Mehrez ◽  
Zied Marrakchi
Keyword(s):  
Routing Algorithm ◽  
Wire Length ◽  
Wave Dynamic ◽  
Placement And Routing ◽  
Power Attacks ◽  
Differential Pair ◽  
Routing Techniques ◽  
Mesh Architecture

The wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-railsignals in WDDL design. We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain they confer. Then, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in tree-based, simple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh architecture, we propose a differential pair routing algorithm that is specific to cluster-based mesh architecture. It achieves perfectly balanced routed signals in terms of wire length and switch number.

Sign in / Sign up

Export Citation Format

Share Document