Improved Device Performance in Nano Scale Transistor: An Extended Drain SOI MOSFET

2016 ◽  
Vol 5 (7) ◽  
pp. M74-M77 ◽  
Author(s):  
Mahsa Mehrad ◽  
Meysam Zareiee
Keyword(s):  
Device Performance ◽  
Soi Mosfet ◽  
Nano Scale

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Characteristic Variations Induced by Random Fluctuation of Source/Drain Lateral Distribution Dopant in Nano-Scale UTB SOI MOSFET

2019 ◽  
Vol 18 (1) ◽  
pp. 77-81
Author(s):  
Linfeng Du ◽  
Hui Deng ◽  
Gang Du ◽  
Ruqi Han ◽  
Shengdong Zhang
Keyword(s):  
Lateral Distribution ◽  
Random Fluctuation ◽  
Soi Mosfet ◽  
Nano Scale ◽  
Utb Soi Mosfet

Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling

1998 ◽  
Vol 45 (5) ◽  
pp. 1017-1025 ◽  
Author(s):  
J.-P. Raskin ◽  
R. Gillon ◽  
Jian Chen ◽  
D. Vanhoenacker-Janvier ◽  
J.-P. Colinge
Keyword(s):  
Performance Optimization ◽  
Device Performance ◽  
Microwave Frequencies ◽  
Soi Mosfet ◽  
Analog Modeling

scholarly journals Sub-Threshold Slope and ON/OFF Current variation in Nano-Scale MOSFETs

2019 ◽  
Author(s):  
Raja N Mir
Keyword(s):  
Three Dimensional ◽  
Device Performance ◽  
Gate Length ◽  
Subthreshold Slope ◽  
Current Ratio ◽  
Nano Scale ◽  
Current Variation ◽  
Mos Device ◽  
Three Dimensional Simulations

The Multi Gate transistors (MGT) have been used to improve the transistor device performance at the nanometer scales. MGTs alleviate many problems in the planar devices due to tighter control of the gate on the channel. In this paper the change in the Fin Architecture and Gate Length of the MOS device, is correlated with the Subthreshold Slope (SS) and ON/OFF current ratio. The study is done by conducting experiments and three-dimensional simulations.

Nano Scale Soi Mosfet Structures and Study of Performance Factors

2010 ◽  
Vol 1 (28) ◽  
pp. 42-47
Author(s):  
Prakash Baviskar ◽  
Sanjeev Jain ◽  
Prasad Vinchurkar
Keyword(s):  
Soi Mosfet ◽  
Performance Factors ◽  
Nano Scale
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