Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling

1998 ◽  
Vol 45 (5) ◽  
pp. 1017-1025 ◽  
Author(s):  
J.-P. Raskin ◽  
R. Gillon ◽  
Jian Chen ◽  
D. Vanhoenacker-Janvier ◽  
J.-P. Colinge
Keyword(s):  
Performance Optimization ◽  
Device Performance ◽  
Microwave Frequencies ◽  
Soi Mosfet ◽  
Analog Modeling

scholarly journals Recent advances in radiation detection technologies enabled by metal-halide perovskites

2021 ◽  
Author(s):  
Tiebin Yang ◽  
Feng Li ◽  
Rongkun Zheng
Keyword(s):  
Gamma Rays ◽  
Performance Optimization ◽  
Radiation Detection ◽  
High Energy ◽  
Device Performance ◽  
High Energy Radiation ◽  
Energy Radiation ◽  
Halide Perovskites ◽  
Alpha Beta ◽  
Detection Technologies

Perovskite halides hold great potential for high-energy radiation detection. Recent advancements in detecting alpha-, beta-, X-, and gamma-rays by perovskite halides are reviewed and an outlook on the device performance optimization is provided.

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Gate length scaling optimization of FinFETs

2018 ◽  
Vol 32 (14) ◽  
pp. 1850176 ◽  
Author(s):  
Shoumian Chen ◽  
Enming Shang ◽  
Shaojian Hu
Keyword(s):  
Work Function ◽  
Leakage Current ◽  
Performance Optimization ◽  
Device Performance ◽  
Optimization Approach ◽  
Gate Length ◽  
Short Channel ◽  
Drive Current ◽  
Channel Effect ◽  
Length Scaling

This paper introduces a device performance optimization approach for the FinFET through optimization of the gate length. As a result of reducing the gate length, the leakage current (I[Formula: see text]) increases, and consequently, the stress along the channel enhances which leads to an increase in the drive current (I[Formula: see text]) of the PMOS. In order to sustain I[Formula: see text], work function is adjusted to offset the effect of the increased stress. Changing the gate length of the transistor yields different drive currents when the leakage current is fixed by adjusting the work function. For a given device, an optimal gate length is found to provide the highest drive current. As an example, for a standard performance device with I[Formula: see text] = 1 nA/um, the best performance I[Formula: see text] = 856 uA/um is at L = 34 nm for 14 nm FinFET and I[Formula: see text] = 1130 uA/um at L = 21 nm for 7 nm FinFET. A 7 nm FinFET will exhibit performance boost of 32% comparing with 14 nm FinFET. However, applying the same method to a 5 nm FinFET, the performance boosting is out of expectance comparing to the 7 nm FinFET, which is due to the severe short-channel-effect and the exhausted channel stress in the FinFET.

The Impacts of Cesl and STI Mechanical Stress Effect on Device Performance for UTBB FD-SOI MOSFET

2020 ◽  
Vol MA2020-02 (68) ◽  
pp. 3612-3612
Author(s):  
Byung-eun Yun ◽  
Yk Hong ◽  
Young-sang Jung ◽  
Youngmok Kim ◽  
Jin-Hong Park ◽  
...  
Keyword(s):  
Mechanical Stress ◽  
Device Performance ◽  
Stress Effect ◽  
Soi Mosfet

Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET

2017 ◽  
Vol 27 (04) ◽  
pp. 1850063 ◽  
Author(s):  
Rajneesh Sharma ◽  
Rituraj S. Rathore ◽  
Ashwani K. Rana
Keyword(s):  
Dielectric Materials ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Effects ◽  
The Impact ◽  
Gate Underlap

The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current ([Formula: see text]). However, the gate underlap also results in reduced ON current ([Formula: see text]) due to increased effective channel length. The use of high-[Formula: see text] material as a spacer region helps to achieve the higher [Formula: see text] but at the cost of increased effective gate capacitance ([Formula: see text]) which degrades the device performance. Thus, the impact of high-[Formula: see text] spacer on the performance of underlap SOI MOSFET (underlap-SOI) is studied in this paper. To fulfil this objective, we have analyzed the performance parameters such as [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text]/[Formula: see text] ratio and intrinsic transistor delay (CV/I) with respect to the variation of device parameters. Various dielectric materials are compared to optimize the [Formula: see text]/[Formula: see text] ratio and CV/I for nanoscale underlap-SOI device. Results suggest that the HfO2 of 10[Formula: see text]nm length is optimum value to enhance device performance. Further, the higher underlap length is needed to offset the exponential increase in [Formula: see text] especially below 20[Formula: see text]nm gate length.

scholarly journals Proposal of High-Temperature-Operation Tolerant SOI MOSFET and Preliminary Study on Device Performance Evaluation

2011 ◽  
Vol 2011 ◽  
pp. 1-8 ◽  
Author(s):  
Yasuhisa Omura
Keyword(s):  
Performance Evaluation ◽  
High Temperature ◽  
Band Gap ◽  
Threshold Voltage ◽  
Thermal Instability ◽  
Device Performance ◽  
Soi Mosfet ◽  
Preliminary Study ◽  
Simulation Results ◽  
High Temperature Operation

We propose a high-temperature-operation (HTOT) SOI MOSFET and show preliminary simulation results of its characteristics. It is demonstrated that HTOT SOI MOSFET operates safely at 700 K with no thermal instability because of its expanded effective bandgap. It is shown that its threshold voltage is higher than that of the conventional SOI MOSFET because its local thin Si regions offer an expanded effective band gap. It is shown that HTOT SOI MOSFET with 1-nm-thick local-thin Si regions is almost insensitive to temperature for (427 C). This confirms that HTOT SOI MOSFET is a promising device for future high-temperature applications.

High Speed GaAs Based Devices on Si Substrates

1986 ◽  
Vol 67 ◽  
Author(s):  
Hadis Morkoc
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
High Speed ◽  
Bipolar Transistors ◽  
Annealing Process ◽  
Current Gain ◽  
Device Performance ◽  
Microwave Frequencies ◽  
Si Substrates ◽  
Cutoff Frequencies ◽  
Oscillation Frequencies

ABSTRACTRemarkably good device performance at both dc and microwave frequencies has recently been obtained from GaAs based devices grown on Si substrates. In GaAs MESFETs on Si, current gain cutoff frequencies and maximum oscillation frequencies of fT = 13.3 GHz and fmax = 30 GHz have been obtained for 1.2μm devices, which is nearly identical to the performance achieved in GaAs on GaAs technology for both direct implant and epitaxial technology. For heterojunction bipolar transistors, current gain cutoff frequencies and maximum oscillation frequencies of fT = 30 GHz and fmax = 11.3 GHz have been obtained for emitter dimensions of 4×20μm2. In GaAs AlGaAs MODFETs. current gain cut-off frequencies of about 15 GHz with lμm gates were obtained on GaAs and Si substrates. The pseudomorphic InGaAs/GaAs MODFETs were also fabricated and found to be comparable to GaAs MODFETs although they should perform better. The structures were also shown to maintain their properties when put through ion implantation and annealing process. Given the performance already demonstrated in GaAs on Si devices and the advantages afforded by this technology, the growth of III-Vs on Si promises to play an important role in the future of heterojunction electronics.

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