scholarly journals Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

2015 ◽  
Vol 4 (6) ◽  
pp. N5067-N5076 ◽  
Author(s):  
F. Roozeboom ◽  
F. van den Bruele ◽  
Y. Creyghton ◽  
P. Poodt ◽  
W. M. M. Kessels
Keyword(s):  
Room Temperature ◽  
Atomic Layer ◽  
High Rate ◽  
Spatial Concept ◽  
Atomic Layer Etching

Atomic Layer Etching of Porous Silicon

1996 ◽  
Vol 452 ◽  
Author(s):  
I. H. Libon ◽  
C. Voelkmann ◽  
V. Petrova-Koch ◽  
F. Koch
Keyword(s):  
Porous Silicon ◽  
Quantum Confinement ◽  
Lower Energy ◽  
Room Temperature ◽  
Size Dependence ◽  
Atomic Layer ◽  
Layer By Layer ◽  
Energy Limit ◽  
First Time ◽  
Atomic Layer Etching

AbstractIn this work we describe the controlled shifting of the PL peak of p+ (10 mΩcm) porous silicon (PoSi) by means of atomic layer etching (ALEP). We hereby study the cluster-size dependence of the PL of this material. By this technique of repeated oxidation by H2O2 and stripping of the oxidized surface layer, we reduced the size of the crystallites layer by layer. In all previous reports the PoSi PL appeared to have a natural lower energy limit of ≈ 1.4 eV. We report for the first time a continuous shift of the PoSi PL peak between 1.01 and 1.20 eV. This observation allows us to draw conclusions for the luminescence mechanism: it proves that geometrical quantum confinement in Si crystallites is responsible for the efficient room-temperature PL in PoSi near the indirect bandgap of c-Si. Together with observations of size-independent PL peaks around 1.6 eV in thermally oxidized samples this result indicates that the PoSi PL cannot be described by one origin alone. Both the existence of molecular centers and the geometrical quantum confinement are valid in their specific range of etching and post-anodic treatment parameters.

scholarly journals HfS2 thin films deposited at room temperature by an emerging technique, solution atomic layer deposition

2021 ◽  
Author(s):  
Yuanyuan Cao ◽  
Sha Zhu ◽  
Julien Bachmann
Keyword(s):  
Thin Films ◽  
Atomic Layer Deposition ◽  
Room Temperature ◽  
Atomic Layer ◽  
Two Dimensional ◽  
Molecular Precursors ◽  
Layer Deposition

The two-dimensional material and semiconducting dichalcogenide hafnium disulfide is deposited at room temperature by atomic layer deposition from molecular precursors dissolved in hexane.

647 Development of a Cerium (III) Nitrate-containing Electrospun Dressing for Mitigating Delayed Eschar Removal

2020 ◽  
Vol 41 (Supplement_1) ◽  
pp. S169-S170
Author(s):  
Angela R Jockheck-Clark ◽  
Cortes Williams ◽  
Christine Kowalczewski ◽  
Jahnabi Roy ◽  
Marc A Thompson ◽  
...  
Keyword(s):  
Room Temperature ◽  
Thermal Injury ◽  
Storage Stability ◽  
Wound Dressings ◽  
High Rate ◽  
Burn Wound ◽  
Burn Treatment ◽  
N Application ◽  
Surgical Interventions ◽  
N Release

Abstract Introduction During periods of delayed burn treatment, cells within the eschar leach toxic and immunomodulatory metabolites that can profoundly impact neighboring tissue. Therefore, to reduce the burn-related morbidities and mortalities that are the result of delayed surgical interventions, electrospinning was utilized to generate a novel cerium (III) nitrate (Ce(III)N) dressing. Previously published work has demonstrated that topical Ce(III)N application changes the eschar morphology, and that tissue beneath the treated eschar was generally healthy and had a high rate of graft acceptance. Methods Ce(III)N was dissolved with polyethylene oxide and spun onto a grounded rotating mandrel. The uni-axially spun mesh was compared to a co-axially electrospun dressing that contained a Ce(III)N core. Dressings were evaluated for topography/morphology, porosity and oxygen permeation using scanning electron microscopy, helium pycnometry, and a gas exchange chamber, respectively. Ce(III)N release rates were evaluated, as well as 60-day storage stability. Results All electrospun dressings contained functional Ce(III)N, with the co-axially spun dressing containing three times the amount of Ce(III)N as the traditionally spun dressing. Uni-axially and co-axially spun nanofibers had diameters of 1487±560 nm and 1071±147 nm, and porosities of 83.9% and 74.1%, respectively. Scaffolds released the majority of Ce(III)N within the first hour of wetting. Conclusions All dressings were capable of a burst of Ce(III)N release and maintained stability when stored at room temperature for 60 days. Applicability of Research to Practice Despite advancement in protective equipment worn by military personnel, the incidence of thermal injury is expected to rise in future conflicts. There are no burn wound dressings that can mitigate the pathophysiological processes associated with delayed burn wound treatment.

RECENT DEVELOPMENTS ON 3D INTEGRATION OF METALLIC SET ONTO CMOS PROCESS FOR MEMORY APPLICATION

2012 ◽  
Vol 11 (04) ◽  
pp. 1240024 ◽  
Author(s):  
N. JOUVET ◽  
M. A. BOUNOUAR ◽  
S. ECOFFEY ◽  
C. NAUENHEIM ◽  
A. BEAUMONT ◽  
...  
Keyword(s):  
Room Temperature ◽  
Memory Cell ◽  
Atomic Layer ◽  
Cmos Process ◽  
3D Integration ◽  
Simulation Tools ◽  
Layer Deposition ◽  
Recent Developments ◽  
Sram Memory ◽  
Electrical Characterizations

This work presents a nanodamascene process for a CMOS back-end-of-line fabrication of metallic single electron transistor(SET), together with the use of simulation tools for the development of a SET SRAM memory cell. We show room temperature electrical characterizations of SETs fabricated on CMOS with relaxed dimensions, and simulations of a SET SRAM memory cell. Using their physical characteristics achievable through the use of atomic layer deposition, it will be demonstrated that it has the potential to operate at temperature up to 398 K, and that power consumption is less than that of equivalent circuit in advanced CMOS technologies. In order to take advantage of both low power SETs and high CMOS drive efficiency, a hybrid 3D SET CMOS circuit is proposed.

Damaged silicon contact layer removal using atomic layer etching for deep-nanoscale semiconductor devices

2013 ◽  
Vol 31 (6) ◽  
pp. 061310 ◽  
Author(s):  
Jong Kyu Kim ◽  
Sung Il Cho ◽  
Sung Ho Lee ◽  
Chan Kyu Kim ◽  
Kyung Suk Min ◽  
...  
Keyword(s):  
Semiconductor Devices ◽  
Atomic Layer ◽  
Contact Layer ◽  
Layer Removal ◽  
Atomic Layer Etching

Understanding time-resolved processes in atomic-layer etching of ultra-thin Al2O3 film using BCl3 and Ar neutral beam

2014 ◽  
Vol 105 (9) ◽  
pp. 093104 ◽  
Author(s):  
Young I. Jhon ◽  
Kyung S. Min ◽  
G. Y. Yeom ◽  
Young Min Jhon
Keyword(s):  
Atomic Layer ◽  
Neutral Beam ◽  
Al2o3 Film ◽  
Time Resolved ◽  
Atomic Layer Etching

Direct Nanoscale Patterning by Atomic Manipulation

1995 ◽  
Vol 380 ◽  
Author(s):  
Craig T. Salling
Keyword(s):  
Scanning Tunneling Microscope ◽  
Room Temperature ◽  
Atomic Layer ◽  
Sample Surface ◽  
Atomic Scale ◽  
Scanning Tunneling ◽  
Nanoscale Patterning ◽  
Direct Patterning ◽  
Scale Structures ◽  
Atomic Manipulation

ABSTRACTThe ability to create atomic-scale structures with the scanning tunneling microscope (STM) plays an important role in the development of a future nanoscale technology. I briefly review the various modes of STM-based fabrication and atomic manipulation. I focus on using a UHV-STM to directly pattern the Si(001) surface by atomic manipulation at room temperature. By carefully adjusting the tip morphology and pulse voltage, a single atomic layer can be removed from the sample surface to define features one atom deep. Segments of individual dimer rows can be removed to create structures with atomically straight edges and with lateral features as small as one dimer wide. Trenches ∼3 nm wide and 2–3 atomic layers deep can be created with less stringent control of patterning parameters. Direct patterning provides a straightforward route to the fabrication of nanoscale test structures under UHV conditions of cleanliness.

(Invited) Volatile Products during Thermal Atomic Layer Etching of Metal Oxides and Elemental Metals

2021 ◽  
Vol MA2021-01 (21) ◽  
pp. 844-844
Author(s):  
Ann Lii-Rosales ◽  
Virginia Johnson ◽  
Sandeep Sharma ◽  
Andrew S Cavanagh ◽  
Steven M George
Keyword(s):  
Metal Oxides ◽  
Atomic Layer ◽  
Volatile Products ◽  
Atomic Layer Etching

Prediction and Validation of the Process Window for Atomic Layer Etching: HF Exposure on TiO2

2021 ◽  
Author(s):  
Suresh Kondati Natarajan ◽  
Austin M. Cano ◽  
Jonathan L. Partridge ◽  
Steven M. George ◽  
Simon D. Elliott
Keyword(s):  
Atomic Layer ◽  
Process Window ◽  
Atomic Layer Etching
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