Prediction and Validation of the Process Window for Atomic Layer Etching: HF Exposure on TiO2

2021 ◽  
Author(s):  
Suresh Kondati Natarajan ◽  
Austin M. Cano ◽  
Jonathan L. Partridge ◽  
Steven M. George ◽  
Simon D. Elliott
Keyword(s):  
Atomic Layer ◽  
Process Window ◽  
Atomic Layer Etching

Applications for Surface Engineering Using Atomic Layer Etching - Invited Paper

2016 ◽  
Vol 255 ◽  
pp. 41-48 ◽  
Author(s):  
John Papalia ◽  
Nathan Marchack ◽  
Robert Bruce ◽  
Hiroyuki Miyazoe ◽  
Sebastian Engelmann ◽  
...  
Keyword(s):  
Surface Engineering ◽  
Process Development ◽  
Semiconductor Industry ◽  
Atomic Layer ◽  
Process Window ◽  
Plasma Parameters ◽  
Unit Process ◽  
Small Pitch ◽  
Irradiation Energy ◽  
Atomic Layer Etching

Over the course of the past few years, the semiconductor industry has continued to invent and innovate profoundly to adhere to Moore’s Law and Dennard scaling. At each of the technology nodes starting with 45nm, new materials and integration techniques, such as high-K & metal gates, double patterning techniques, and now 3D FinFet / Trigate device geometries are being introduced in order to maintain device performance. This places a large burden on unit process development to accommodate and deliver advanced process capability and is growing the need for the ultimate etch solution: etching with atomic layer precision. Atomic layer etching is a promising path to answer the processing demands of thin high mobility channel devices on the angstrom scale. Self-limiting reactions, discrete reaction & activation steps, or extremely low ion energy etch plasmas are some of the pathways being pursued for precise sub-nanometer material removal. In this invited paper, previously published in SPIE, the ability to achieve atomic layer etch precision is reviewed in detail for a variety of material sets and implementation methods. For a cyclic approach most similar to a reverse ALD scheme, the process window to achieve a truly self-limited atomic layer etch process is identified and the limitations as a function of controlling the adsorption step, the irradiation energy, and the reaction process are examined. Alternative approaches, including processes to enable pseudo-ALE precision, are then introduced and results from their application investigated. While these new plasma-enhanced atomic layer etch (PE-ALE) processes show encouraging results, most patterning applications are best realized by optimizations through discharge chemistry and/or plasma parameters. Significant improvements however were obtained when applying PE-ALE approaches to small pitch patterns. In particular the increased selectivity to OPL seems to offer a potential benefit for patterning high aspect ratio features.

Damaged silicon contact layer removal using atomic layer etching for deep-nanoscale semiconductor devices

2013 ◽  
Vol 31 (6) ◽  
pp. 061310 ◽  
Author(s):  
Jong Kyu Kim ◽  
Sung Il Cho ◽  
Sung Ho Lee ◽  
Chan Kyu Kim ◽  
Kyung Suk Min ◽  
...  
Keyword(s):  
Semiconductor Devices ◽  
Atomic Layer ◽  
Contact Layer ◽  
Layer Removal ◽  
Atomic Layer Etching

Understanding time-resolved processes in atomic-layer etching of ultra-thin Al2O3 film using BCl3 and Ar neutral beam

2014 ◽  
Vol 105 (9) ◽  
pp. 093104 ◽  
Author(s):  
Young I. Jhon ◽  
Kyung S. Min ◽  
G. Y. Yeom ◽  
Young Min Jhon
Keyword(s):  
Atomic Layer ◽  
Neutral Beam ◽  
Al2o3 Film ◽  
Time Resolved ◽  
Atomic Layer Etching

(Invited) Volatile Products during Thermal Atomic Layer Etching of Metal Oxides and Elemental Metals

2021 ◽  
Vol MA2021-01 (21) ◽  
pp. 844-844
Author(s):  
Ann Lii-Rosales ◽  
Virginia Johnson ◽  
Sandeep Sharma ◽  
Andrew S Cavanagh ◽  
Steven M George
Keyword(s):  
Metal Oxides ◽  
Atomic Layer ◽  
Volatile Products ◽  
Atomic Layer Etching

scholarly journals Electrical Characterization of Postmetal Annealed Ultrathin TiN Gate Electrodes in Si MOS Capacitors

2016 ◽  
Vol 2016 ◽  
pp. 1-4 ◽  
Author(s):  
Z. N. Khan ◽  
S. Ahmed ◽  
M. Ali
Keyword(s):  
Electrical Characterization ◽  
Atomic Layer ◽  
Device Fabrication ◽  
Process Window ◽  
Gate Stacks ◽  
Mos Capacitors ◽  
Hafnium Silicate ◽  
Gate Electrodes ◽  
Layer Deposition ◽  
Tin Metal

Focusing on sub-10 nm Silicon CMOS device fabrication technology, we have incorporated ultrathin TiN metal gate electrode in Hafnium Silicate (HfSiO) based metal-oxide capacitors (MOSCAP) with carefully chosen Atomic Layer Deposition (ALD) process parameters. Gate element of the device has undergone a detailed postmetal annealed sequence ranging from 100°C to 1000°C. The applicability of ultrathin TiN on gate electrodes is established through current density versus voltage (J-V), resistance versus temperature (R-T), and permittivity versus temperature analysis. A higher process window starting from 600°C was intentionally chosen to understand the energy efficient behavior expected from ultrathin gate metallization and its unique physical state with shrinking thickness. The device characteristics in form of effective electronic mobility as a function of inverse charge density were also found better than those conventional gate stacks used for EOT scaling.

scholarly journals Predicting synergy in atomic layer etching

2017 ◽  
Vol 35 (5) ◽  
pp. 05C302 ◽  
Author(s):  
Keren J. Kanarik ◽  
Samantha Tan ◽  
Wenbing Yang ◽  
Taeseung Kim ◽  
Thorsten Lill ◽  
...  
Keyword(s):  
Atomic Layer ◽  
Atomic Layer Etching

Thermal Atomic Layer Etching of Silicon Using O2, HF, and Al(CH3)3 as the Reactants

2018 ◽  
Vol 30 (23) ◽  
pp. 8465-8475 ◽  
Author(s):  
Aziz I. Abdulagatov ◽  
Steven M. George
Keyword(s):  
Atomic Layer ◽  
Atomic Layer Etching

scholarly journals Fluorocarbon assisted atomic layer etching of SiO2 and Si using cyclic Ar/C4F8 and Ar/CHF3 plasma

2016 ◽  
Vol 34 (1) ◽  
pp. 01B101 ◽  
Author(s):  
Dominik Metzler ◽  
Chen Li ◽  
Sebastian Engelmann ◽  
Robert L. Bruce ◽  
Eric A. Joseph ◽  
...  
Keyword(s):  
Atomic Layer ◽  
Atomic Layer Etching
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