Study on Defect Reduction and Yield Improvement of MIM Al Deposition Process

2019 ◽  
Vol 44 (1) ◽  
pp. 791-796
Author(s):  
Vincent Chang ◽  
Athics Gu ◽  
Terry Li ◽  
Ji-Wei Zhang ◽  
Jian-Yong Jiang ◽  
...  
Keyword(s):  
Deposition Process ◽  
Yield Improvement ◽  
Defect Reduction

Improve the Mechanisms Product Yield through Cycle Time Optimization

2013 ◽  
Vol 433-435 ◽  
pp. 2409-2412
Author(s):  
Fei Xiong ◽  
Jin Yao
Keyword(s):  
Cycle Time ◽  
Product Yield ◽  
Driving Cycle ◽  
Manufacturing Environment ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Management Level ◽  
Time Optimization ◽  
Quality Product ◽  
Made In

In mechanisms manufacturing environment, factory management level is always trying to achieve higher product yield to ship more quality product to the customers. In this paper, we will show the yield improvement based on cycle time reduces. Yield organization has established excellent systems for driving defect reduction. Established a clear set of core principles that would help drive a new way of driving cycle time improvement. Discuss the key findings captured through yield benchmarking activities. There are three core principles outlined above and the associated changes made in manufacturing to embrace these principles.

Crown Defect Reduction and Cp Yield Improvement for High Voltage Power Management IC Product

2019 ◽  
Vol 27 (1) ◽  
pp. 377-382
Author(s):  
Guan-Qun Zhang ◽  
Athics Gu ◽  
Yi-Hui Lin ◽  
Peng Sun ◽  
Jiwei Zhang ◽  
...  
Keyword(s):  
Power Management ◽  
High Voltage ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Power Management Ic

Targeted Defect Analysis for Yield Improvement

2002 ◽  
Author(s):  
Luis Andrade ◽  
Timothy Bynum ◽  
Richard Doyle ◽  
Brian Flaherty ◽  
David Grammer ◽  
...  
Keyword(s):  
Learning Process ◽  
Optimum Allocation ◽  
Defect Analysis ◽  
Yield Losses ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Manufacturing Line ◽  
Technology Products ◽  
Short And Long Term

Abstract Defect analysis and reduction is a focus in all wafer fabs, but there are many approaches to minimizing defect related yield losses. This paper describes the analysis for defect learning and our methodology for defect reduction within our manufacturing line including wafer selection, optimum allocation of engineering resources, details of the learning process, and objectives (both short and long term) of the defect analysis. The focus of the paper is on our 140nm DRAM technology products.

Arc Suppression and Defect Reduction in Semiconductor Metallization

1998 ◽  
Vol 510 ◽  
Author(s):  
Xiangbing Li ◽  
David Loo ◽  
Brad Stimson ◽  
Scott Seamons ◽  
Murali Narasimhan
Keyword(s):  
Deposition Rate ◽  
Adverse Impact ◽  
Film Properties ◽  
High Quality ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Process Characterization ◽  
Sputtering Power ◽  
Rate Loss ◽  
The Impact

AbstractSuppression of arcing between the target and plasma during PVD is a key issue for defect reduction, yield improvement and high quality metallization in microelectronics manufacturing. An integrated mini sparcle product has been designed for Endura HP PVD™ sputtering sources. Characteristics of arcing and mechanisms for suppression are discussed here. Process characterization with Ti, TiN and Al sputtering proves that the arc suppression unit has little adverse impact on film properties. The uniformity of reactive sputtered TiN is improved with arc suppression. Marathon evaluation indicates significant reduction in TiN defect and Interconnect metal stack defect. The study of the application for a wide variety of materials (Al, Ti, TiN, SiW, Si) establishes a correlation between deposition rate loss and sputtering power and this relation is found to be almost independent of the materials sputtered. The impact on throughput for typical metal stack is also presented in this paper.

STI Crater Defect Reduction for Semiconductor Device Yield Improvement

2013 ◽  
Vol 26 (3) ◽  
pp. 335-338
Author(s):  
Li Liang ◽  
Rao Xue Song ◽  
Lu Wei ◽  
See Alex
Keyword(s):  
Semiconductor Device ◽  
Yield Improvement ◽  
Defect Reduction

Reaction couples of ceramic thin films prepared by CVD

1988 ◽  
Vol 46 ◽  
pp. 798-799
Author(s):  
D.W. Susnitzky ◽  
S.R. Summerfelt ◽  
C.B. Carter
Keyword(s):  
Thin Film ◽  
Vapor Deposition ◽  
Chemical Vapor ◽  
Deposition Process ◽  
Solid State Reactions ◽  
Spatial Distributions ◽  
Diffusion Couples ◽  
Kinetics Studies ◽  
Ceramic Thin Films ◽  
Initial Stage

Solid-state reactions have traditionally been studied in the form of diffusion couples. This ‘bulk’ approach has been modified, for the specific case of the reaction between NiO and Al2O3, by growing NiAl2O4 (spinel) from electron-transparent Al2O3 TEM foils which had been exposed to NiO vapor at 1415°C. This latter ‘thin-film’ approach has been used to characterize the initial stage of spinel formation and to produce clean phase boundaries since further TEM preparation is not required after the reaction is completed. The present study demonstrates that chemical-vapor deposition (CVD) can be used to deposit NiO particles, with controlled size and spatial distributions, onto Al2O3 TEM specimens. Chemical reactions do not occur during the deposition process, since CVD is a relatively low-temperature technique, and thus the NiO-Al2O3 interface can be characterized. Moreover, a series of annealing treatments can be performed on the same sample which allows both Ni0-NiAl2O4 and NiAl2O4-Al2O3 interfaces to be characterized and which therefore makes this technique amenable to kinetics studies of thin-film reactions.

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