Defect reduction strategies for process control and yield improvement

1991 ◽  
Author(s):  
Douglas R. Liljegren
Keyword(s):  
Process Control ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Reduction Strategies

Improve the Mechanisms Product Yield through Cycle Time Optimization

2013 ◽  
Vol 433-435 ◽  
pp. 2409-2412
Author(s):  
Fei Xiong ◽  
Jin Yao
Keyword(s):  
Cycle Time ◽  
Product Yield ◽  
Driving Cycle ◽  
Manufacturing Environment ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Management Level ◽  
Time Optimization ◽  
Quality Product ◽  
Made In

In mechanisms manufacturing environment, factory management level is always trying to achieve higher product yield to ship more quality product to the customers. In this paper, we will show the yield improvement based on cycle time reduces. Yield organization has established excellent systems for driving defect reduction. Established a clear set of core principles that would help drive a new way of driving cycle time improvement. Discuss the key findings captured through yield benchmarking activities. There are three core principles outlined above and the associated changes made in manufacturing to embrace these principles.

Study on Defect Reduction and Yield Improvement of MIM Al Deposition Process

2019 ◽  
Vol 44 (1) ◽  
pp. 791-796
Author(s):  
Vincent Chang ◽  
Athics Gu ◽  
Terry Li ◽  
Ji-Wei Zhang ◽  
Jian-Yong Jiang ◽  
...  
Keyword(s):  
Deposition Process ◽  
Yield Improvement ◽  
Defect Reduction

Crown Defect Reduction and Cp Yield Improvement for High Voltage Power Management IC Product

2019 ◽  
Vol 27 (1) ◽  
pp. 377-382
Author(s):  
Guan-Qun Zhang ◽  
Athics Gu ◽  
Yi-Hui Lin ◽  
Peng Sun ◽  
Jiwei Zhang ◽  
...  
Keyword(s):  
Power Management ◽  
High Voltage ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Power Management Ic

Targeted Defect Analysis for Yield Improvement

2002 ◽  
Author(s):  
Luis Andrade ◽  
Timothy Bynum ◽  
Richard Doyle ◽  
Brian Flaherty ◽  
David Grammer ◽  
...  
Keyword(s):  
Learning Process ◽  
Optimum Allocation ◽  
Defect Analysis ◽  
Yield Losses ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Manufacturing Line ◽  
Technology Products ◽  
Short And Long Term

Abstract Defect analysis and reduction is a focus in all wafer fabs, but there are many approaches to minimizing defect related yield losses. This paper describes the analysis for defect learning and our methodology for defect reduction within our manufacturing line including wafer selection, optimum allocation of engineering resources, details of the learning process, and objectives (both short and long term) of the defect analysis. The focus of the paper is on our 140nm DRAM technology products.

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