Defect reduction methodologies: pellicle yield improvement

1993 ◽  
Author(s):  
Susan V. Daugherty
Keyword(s):  
Yield Improvement ◽  
Defect Reduction

Improve the Mechanisms Product Yield through Cycle Time Optimization

2013 ◽  
Vol 433-435 ◽  
pp. 2409-2412
Author(s):  
Fei Xiong ◽  
Jin Yao
Keyword(s):  
Cycle Time ◽  
Product Yield ◽  
Driving Cycle ◽  
Manufacturing Environment ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Management Level ◽  
Time Optimization ◽  
Quality Product ◽  
Made In

In mechanisms manufacturing environment, factory management level is always trying to achieve higher product yield to ship more quality product to the customers. In this paper, we will show the yield improvement based on cycle time reduces. Yield organization has established excellent systems for driving defect reduction. Established a clear set of core principles that would help drive a new way of driving cycle time improvement. Discuss the key findings captured through yield benchmarking activities. There are three core principles outlined above and the associated changes made in manufacturing to embrace these principles.

Study on Defect Reduction and Yield Improvement of MIM Al Deposition Process

2019 ◽  
Vol 44 (1) ◽  
pp. 791-796
Author(s):  
Vincent Chang ◽  
Athics Gu ◽  
Terry Li ◽  
Ji-Wei Zhang ◽  
Jian-Yong Jiang ◽  
...  
Keyword(s):  
Deposition Process ◽  
Yield Improvement ◽  
Defect Reduction

Crown Defect Reduction and Cp Yield Improvement for High Voltage Power Management IC Product

2019 ◽  
Vol 27 (1) ◽  
pp. 377-382
Author(s):  
Guan-Qun Zhang ◽  
Athics Gu ◽  
Yi-Hui Lin ◽  
Peng Sun ◽  
Jiwei Zhang ◽  
...  
Keyword(s):  
Power Management ◽  
High Voltage ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Power Management Ic

Targeted Defect Analysis for Yield Improvement

2002 ◽  
Author(s):  
Luis Andrade ◽  
Timothy Bynum ◽  
Richard Doyle ◽  
Brian Flaherty ◽  
David Grammer ◽  
...  
Keyword(s):  
Learning Process ◽  
Optimum Allocation ◽  
Defect Analysis ◽  
Yield Losses ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Manufacturing Line ◽  
Technology Products ◽  
Short And Long Term

Abstract Defect analysis and reduction is a focus in all wafer fabs, but there are many approaches to minimizing defect related yield losses. This paper describes the analysis for defect learning and our methodology for defect reduction within our manufacturing line including wafer selection, optimum allocation of engineering resources, details of the learning process, and objectives (both short and long term) of the defect analysis. The focus of the paper is on our 140nm DRAM technology products.

Arc Suppression and Defect Reduction in Semiconductor Metallization

1998 ◽  
Vol 510 ◽  
Author(s):  
Xiangbing Li ◽  
David Loo ◽  
Brad Stimson ◽  
Scott Seamons ◽  
Murali Narasimhan
Keyword(s):  
Deposition Rate ◽  
Adverse Impact ◽  
Film Properties ◽  
High Quality ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Process Characterization ◽  
Sputtering Power ◽  
Rate Loss ◽  
The Impact

AbstractSuppression of arcing between the target and plasma during PVD is a key issue for defect reduction, yield improvement and high quality metallization in microelectronics manufacturing. An integrated mini sparcle product has been designed for Endura HP PVD™ sputtering sources. Characteristics of arcing and mechanisms for suppression are discussed here. Process characterization with Ti, TiN and Al sputtering proves that the arc suppression unit has little adverse impact on film properties. The uniformity of reactive sputtered TiN is improved with arc suppression. Marathon evaluation indicates significant reduction in TiN defect and Interconnect metal stack defect. The study of the application for a wide variety of materials (Al, Ti, TiN, SiW, Si) establishes a correlation between deposition rate loss and sputtering power and this relation is found to be almost independent of the materials sputtered. The impact on throughput for typical metal stack is also presented in this paper.

STI Crater Defect Reduction for Semiconductor Device Yield Improvement

2013 ◽  
Vol 26 (3) ◽  
pp. 335-338
Author(s):  
Li Liang ◽  
Rao Xue Song ◽  
Lu Wei ◽  
See Alex
Keyword(s):  
Semiconductor Device ◽  
Yield Improvement ◽  
Defect Reduction

Defect reduction in oxygen implanted silicon-on-insulator material during high-temperature annealing

1989 ◽  
Vol 47 ◽  
pp. 604-605
Author(s):  
P. Roitman ◽  
B. Cordts ◽  
S. Visitserngtrakul ◽  
S.J. Krause
Keyword(s):  
High Temperature ◽  
Annealing Temperature ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing ◽  
High Current ◽  
Defect Reduction ◽  
Annealing Step ◽  
Multiple Cycle ◽  
Defect Densities

Synthesis of a thin, buried dielectric layer to form a silicon-on-insulator (SOI) material by high dose oxygen implantation (SIMOX – Separation by IMplanted Oxygen) is becoming an important technology due to the advent of high current (200 mA) oxygen implanters. Recently, reductions in defect densities from 109 cm−2 down to 107 cm−2 or less have been reported. They were achieved with a final high temperature annealing step (1300°C – 1400°C) in conjunction with: a) high temperature implantation or; b) channeling implantation or; c) multiple cycle implantation. However, the processes and conditions for reduction and elimination of precipitates and defects during high temperature annealing are not well understood. In this work we have studied the effect of annealing temperature on defect and precipitate reduction for SIMOX samples which were processed first with high temperature, high current implantation followed by high temperature annealing.

Defect Reduction in Ring Blank Casting Through Design of Experiments

2015 ◽  
Vol 9 (6) ◽  
pp. 536 ◽  
Author(s):  
P. Kannan ◽  
K. Balasubramanian ◽  
R. Vinayagamoorthy
Keyword(s):  
Design Of Experiments ◽  
Defect Reduction ◽  
Ring Blank
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