Selective Incorporation of Colloidal Nanocrystals in Nanopatterned SiO[sub 2] Layer for Nanocrystal Memory Device

2010 ◽  
Vol 13 (3) ◽  
pp. K19 ◽  
Author(s):  
Il Seo ◽  
Do-Joong Lee ◽  
Quanli Hu ◽  
Chang-Woo Kwon ◽  
Kipil Lim ◽  
...  
2000 ◽  
Vol 609 ◽  
Author(s):  
Seung Jae Baik ◽  
Koeng Su Lim

ABSTRACTTwo-dimensional (2D) Si quantum dot array was fabricated by oxidation of microcrystalline Si film deposited by photo chemical vapor deposition (photo-CVD). Average size of Si quantum dot was estimated to be 2.4nm and dot density 7 ∼ 8 ×1011 cm−2. Nanocrystal memory device with this 2D quantum dot array demonstrated negative differential resistance characteristics and single charge tunneling phenomena, which was observed as stepwise decrease of gate transconductance. Interface states at the oxidized surface of quantum dots were assumed to explain temperature dependence characteristics. This new process is adequate for functional device application of nanocrystal metal-oxide-semiconductor (MOS) memory.


2003 ◽  
Vol 50 (10) ◽  
pp. 2067-2072 ◽  
Author(s):  
Jong Jin Lee ◽  
Xuguang Wang ◽  
Weiping Bai ◽  
Nan Lu ◽  
Dim-Lee Kwong

2003 ◽  
Vol 24 (5) ◽  
pp. 345-347 ◽  
Author(s):  
Zengtao Liu ◽  
Chungho Lee ◽  
V. Narayanan ◽  
G. Pei ◽  
E.C. Kan

2010 ◽  
Vol 1250 ◽  
Author(s):  
Panagiotis Dimitrakis ◽  
Eleftherios Iliopoulos ◽  
Pascal Normand

AbstractThe growth of GaN-QDs by radio frequency plasma assisted molecular beam deposition (RF-MBD) on thin SiO2 films for non-volatile memories (NVM) applications is demonstrated. Thermal budget modification during the deposition allows tuning of the size and density of the QDs. Preliminary electrical characterization of GaN-QD MOS devices reveals efficient electron injection at very low voltages from the Si accumulation layer to the QDs. The observed limitation in hole injection relates adequately to the energy band diagram of the structure.


2006 ◽  
Vol 05 (04n05) ◽  
pp. 565-570 ◽  
Author(s):  
M. Y. CHAN ◽  
P. S. LEE

Silicon ( Si ) nanocrystals have been considered a good candidate for flash memory device and nanophotonic applications. The fabrication of nanocrystal memory is to form uniform, small size and high density quantum dots. In this study, nanometer-scale silicon quantum dots have been fabricated on ultrathin silicon oxide layer using amorphous silicon (a- Si ) deposition followed by various annealing treatments. The a- Si layers were crystallized using furnace annealing, laser annealing and rapid thermal annealing (RTA). After annealing to form nanometer-sized crystallites, silicon wet etch was carried out to isolate the nanocrystals. The size, uniformity and density of the nanocrystals were successfully controlled by different annealing treatments. The mean dot height and mean dot diameter is 1–5 nm and 2–5 nm, respectively. Lateral growth of the silicon dots was further controlled by systemic variations of the annealing conditions. It is found that the annealed a- Si films exhibit room temperature visible photoluminescence (PL) resulting from the formation of nanometer-sized crystallites. Selective wet etch and Secco-etch treatment increased the PL efficiency that is useful for nanophotonics applications. The feasibility of quantum dot formation using ultra thin amorphous Si films is demonstrated in this work.


2007 ◽  
Vol 90 (13) ◽  
pp. 132102 ◽  
Author(s):  
F. M. Yang ◽  
T. C. Chang ◽  
P. T. Liu ◽  
P. H. Yeh ◽  
Y. C. Yu ◽  
...  

2006 ◽  
Vol 258-260 ◽  
pp. 531-541 ◽  
Author(s):  
A. Claverie ◽  
Caroline Bonafos ◽  
G. Ben Assayag ◽  
S. Schamm ◽  
N. Cherkashin ◽  
...  

Nanocrystal memories are attractive candidate for the development of non volatile memory devices for deep submicron technologies. In a nanocrystal memory device, a 2D network of isolated nanocrystals is buried in the gate dielectric of a MOS and replaces the classical polysilicon layer used in floating gate (flash) memories. Recently, we have demonstrated a route to fabricate these devices at low cost by using ultra low energy ion implantation. Obviously, all the electrical characteristics of the device depend on the characteristics of the nanocrystal population (sizes and densities) but also on their exact location with respect to the gate and channel of the MOS transistor. It is the goal of this paper to report on the main materials science aspects of the fabrication of 2D arrays of Si nanocrystals in thin SiO2 layers and at tunable distances from their SiO2/interfaces.


2009 ◽  
Vol 1160 ◽  
Author(s):  
Huimei Zhou ◽  
Jianlin Liu

AbstractSelf-aligned TiSi2 coated Si nanocrystal nonvolatile memory is fabricated. This kind of MOSFET memory device is not only thermally stable, but also shows better performance in charge storage capacity, writing, erasing speed and retention characteristics. This indicates that CMOS compatible silicidation process to fabricate TiSi2 coated Si nanocrystal memory is promising in memory device applications.


2003 ◽  
Vol 66 (1-4) ◽  
pp. 33-38 ◽  
Author(s):  
Vincent Ho ◽  
M.S. Tay ◽  
C.H. Moey ◽  
L.W. Teo ◽  
W.K. Choi ◽  
...  

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