Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric

2003 ◽  
Vol 50 (10) ◽  
pp. 2067-2072 ◽  
Author(s):  
Jong Jin Lee ◽  
Xuguang Wang ◽  
Weiping Bai ◽  
Nan Lu ◽  
Dim-Lee Kwong
Keyword(s):  
Experimental Investigation ◽  
Memory Device ◽  
High K ◽  
Si Nanocrystal ◽  
Nanocrystal Memory

Performance enhancement of TiSi2 coated Si nanocrystal memory device

2009 ◽  
Vol 1160 ◽  
Author(s):  
Huimei Zhou ◽  
Jianlin Liu
Keyword(s):  
Nonvolatile Memory ◽  
Storage Capacity ◽  
Performance Enhancement ◽  
Memory Device ◽  
Charge Storage ◽  
Si Nanocrystal ◽  
Device Applications ◽  
Retention Characteristics ◽  
Cmos Compatible ◽  
Nanocrystal Memory

AbstractSelf-aligned TiSi2 coated Si nanocrystal nonvolatile memory is fabricated. This kind of MOSFET memory device is not only thermally stable, but also shows better performance in charge storage capacity, writing, erasing speed and retention characteristics. This indicates that CMOS compatible silicidation process to fabricate TiSi2 coated Si nanocrystal memory is promising in memory device applications.

Self-aligned TiSi2/Si Hetero-nanocrystal Nonvolatile Memory

2007 ◽  
Vol 997 ◽  
Author(s):  
Yan Zhu ◽  
Bei Li ◽  
Jianlin Liu
Keyword(s):  
Retention Time ◽  
Nonvolatile Memory ◽  
Memory Device ◽  
Charge Storage ◽  
Si Nanocrystals ◽  
Nonvolatile Memory Device ◽  
Si Nanocrystal ◽  
Nanocrystal Memory

AbstractThis work describes a novel nonvolatile memory device with self-aligned TiSi2/Si hetero-nanocrystal charge storage nodes. The TiSi2/Si hetero-nanocrystals can be readily fabricated using industrial standard self-aligned silicidation technique based on Si nanocrystals deposited on ultra-thin tunnel oxide with LPCVD. As compared with a Si nanocrystal memory device, a TiSi2/Si hetero-nanocrystal memory device exhibits faster programming and erasing, and longer retention time.

Si Nanocrystal Memory Cell with Room-Temperature Single Electron Effects

2001 ◽  
Vol 40 (Part 1, No. 2A) ◽  
pp. 447-451 ◽  
Author(s):  
Ilgweon Kim ◽  
Sangyeon Han ◽  
Kwangseok Han ◽  
Jongho Lee ◽  
Hyungcheol Shin
Keyword(s):  
Room Temperature ◽  
Memory Cell ◽  
Single Electron ◽  
Si Nanocrystal ◽  
Nanocrystal Memory ◽  
Electron Effects

scholarly journals Nb2O5 and Ti-Doped Nb2O5 Charge Trapping Nano-Layers Applied in Flash Memory

Nanomaterials ◽  
2018 ◽  
Vol 8 (10) ◽  
pp. 799 ◽  
Author(s):  
Jer Wang ◽  
Chyuan Kao ◽  
Chien Wu ◽  
Chun Lin ◽  
Chih Lin
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Dielectric Constants ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Hysteresis Curve ◽  
Band Shift ◽  
K Value ◽  
High K

High-k material charge trapping nano-layers in flash memory applications have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants. In addition, Ti-doped high-k materials can improve memory device performance, such as leakage current reduction, k-value enhancement, and breakdown voltage increase. In this study, the structural and electrical properties of different annealing temperatures on the Nb2O5 and Ti-doped Nb2O5(TiNb2O7) materials used as charge-trapping nano-layers in metal-oxide-high k-oxide-semiconductor (MOHOS)-type memory were investigated using X-ray diffraction (XRD) and atomic force microscopy (AFM). Analysis of the C-V hysteresis curve shows that the flat-band shift (∆VFB) window of the TiNb2O7 charge-trapping nano-layer in a memory device can reach as high as 6.06 V. The larger memory window of the TiNb2O7 nano-layer is because of a better electrical and structural performance, compared to the Nb2O5 nano-layer.

Cycling-Induced Peak-Like Interface State Generation in Si-Nanocrystal Memory Devices

2012 ◽  
Vol 33 (12) ◽  
pp. 1705-1707 ◽  
Author(s):  
Dandan Jiang ◽  
Manhong Zhang ◽  
Zongliang Huo ◽  
Zhong Sun ◽  
Yong Wang ◽  
...  
Keyword(s):  
Interface State ◽  
Memory Devices ◽  
Si Nanocrystal ◽  
State Generation ◽  
Nanocrystal Memory

Selective Incorporation of Colloidal Nanocrystals in Nanopatterned SiO[sub 2] Layer for Nanocrystal Memory Device

2010 ◽  
Vol 13 (3) ◽  
pp. K19 ◽  
Author(s):  
Il Seo ◽  
Do-Joong Lee ◽  
Quanli Hu ◽  
Chang-Woo Kwon ◽  
Kipil Lim ◽  
...  
Keyword(s):  
Memory Device ◽  
Colloidal Nanocrystals ◽  
Selective Incorporation ◽  
Nanocrystal Memory
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