Investigation of Conducting Oxide and Metal Electrode Work Functions on Lanthanum Silicate High-k Dielectric

2019 ◽  
Vol 11 (4) ◽  
pp. 607-612
Author(s):  
Hee Young Lee ◽  
Daniel J. Lichtenwalner ◽  
Jesse S. Jur ◽  
Angus I. Kingon
2019 ◽  
Vol 3 (3) ◽  
pp. 245-252 ◽  
Author(s):  
Dan Lichtenwalner ◽  
Jesse S. Jur ◽  
Angus I. Kingon ◽  
Steven Novak ◽  
Veena Misra

2019 ◽  
Vol 6 (1) ◽  
pp. 149-156
Author(s):  
Jesse S. Jur ◽  
Daniel Lichtenwalner ◽  
Angus Kingon

2021 ◽  
Author(s):  
Dharmender Kumar ◽  
Kaushal Nigam

Abstract This paper investigates the impact of lowK and high-K dielectric pockets on DC characteristics, analog/RF, and linearity performance of dual material stack gate oxide-tunnel field-effect transistor (DMSGODP-TFET). For this, a stack gate oxide with workfunction is considered to enhance the ON-state current (ION ), lower ambipolar current (Iamb) and lower the subthreshold swing. For this case, the gate electrode is tri-segmented, named as tunnel gate (M1), control gate (M2) and auxiliary gate (M3) with different gate lengths (L1, L2, L3) and work functions (φ1, φ2, φ3), respectively. To maintain dual-work functionality, the possible combinations of these work functions are considered. Technology computer-aided design (TCAD) simulations are performed and noted that the workfunction combination (φ1 = φ3 < φ2) outperforms as compared to other combinations. Where φ1 on the source side is used to enhance the ION , while φ3 (equal to φ1) is used on the drain side to minimize the Iamb. To further enhance the device performance, a high-K dielectric pocket is considered at the drain junction to suppress the Iamb whereas, a low-K dielectric pocket is employed at the source junction to enhance the ION . Moreover, length of gate segments, dielectric pocket height, and thickness are optimized to achieve a better switching ratio, subthreshold swing (SS) and reduce the Iamb which helps in the gain of device and design of analog/RF circuits. The proposed device as compared to dual material control gate-dielectric pocket-TFET (DMCG-DP-TFET) with SiO2 gate oxide shows improvement in ION /IOF F (∼ 4.23 times), 84 % increase in transconductance (gm), 136 % increase in cut-off frequency (fT ), 126 % increase in gain bandwidth product (GBP), point subthreshold swing (15.8 mV/decade) and other significant improvements in linearity figure of merits (FOMs) making the proposed device useful for low power switching, analog/RF and linearity applications.


2017 ◽  
Vol 30 (4) ◽  
pp. 511-548 ◽  
Author(s):  
Albena Paskaleva ◽  
Dencho Spassov ◽  
Danijel Dankovic

In this paper conduction mechanisms which could govern the electron transport through high-k dielectrics are summarized. The influence of various factors - the type of high-k dielectric and its thickness; the doping with a certain element; the type of metal electrode as well as the measurement conditions (bias, polarity and temperature), on the leakage currents and dominant conduction mechanisms have been considered. Practical hints how to consider different conduction mechanisms and to differentiate between them are given. The paper presents an approach to assess important trap parameters from investigation of dominant conduction mechanisms.


2008 ◽  
Vol 55 (1) ◽  
pp. 8-20 ◽  
Author(s):  
Byoung Hun Lee ◽  
Seung Chul Song ◽  
Rino Choi ◽  
Paul Kirsch

2008 ◽  
Vol 1073 ◽  
Author(s):  
Daniel J Lichtenwalner ◽  
Rahul Suri ◽  
Veena Misra

ABSTRACTThe properties of lanthanum silicate (LaSiOx) gate stacks on GaAs substrates have been examined, comparing different GaAs pretreatments; namely a) as-received, b) HCl-treated, and c) sulphur-treated. X-ray photoelectron spectroscopy of the As 3d, Ga 3d, and Ga 2p binding energy peaks were used to reveal the chemical nature of the stacks. After a 400 °C in situ anneal in 10−6 torr pO2, the LaSiOx chemically reduces the As oxides from the as-received GaAs, while Ga oxide species remain. HCl and S-treated GaAs similarly show no As oxides, and a much smaller degree of Ga oxides than the as-received case. The Ga-S bonding may be responsible for lowering the tendency towards Ga oxidation for the S-treated case. On p-type, Zn-doped GaAs, 3.0 nm lanthanum silicate films produce MOS device EOT values of 2.38 nm, 1.51 nm, and 1.37 nm, on as-received, HCl-treated, and S-treated substrates, respectively. The high EOT for the as-received GaAs corresponds to the thicker Ga oxide and elemental As at the interface. The decreases in both Ga oxide and elemental As at the interface of the S-treated stack appears to be related to it having the lowest EOT devices.


2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.


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