Reliability and Stability Issues for Lanthanum Silicate as a High-K Dielectric

2019 ◽  
Vol 3 (3) ◽  
pp. 245-252 ◽  
Author(s):  
Dan Lichtenwalner ◽  
Jesse S. Jur ◽  
Angus I. Kingon ◽  
Steven Novak ◽  
Veena Misra
2019 ◽  
Vol 6 (1) ◽  
pp. 149-156
Author(s):  
Jesse S. Jur ◽  
Daniel Lichtenwalner ◽  
Angus Kingon

2019 ◽  
Vol 11 (4) ◽  
pp. 607-612
Author(s):  
Hee Young Lee ◽  
Daniel J. Lichtenwalner ◽  
Jesse S. Jur ◽  
Angus I. Kingon

2008 ◽  
Vol 1073 ◽  
Author(s):  
Daniel J Lichtenwalner ◽  
Rahul Suri ◽  
Veena Misra

ABSTRACTThe properties of lanthanum silicate (LaSiOx) gate stacks on GaAs substrates have been examined, comparing different GaAs pretreatments; namely a) as-received, b) HCl-treated, and c) sulphur-treated. X-ray photoelectron spectroscopy of the As 3d, Ga 3d, and Ga 2p binding energy peaks were used to reveal the chemical nature of the stacks. After a 400 °C in situ anneal in 10−6 torr pO2, the LaSiOx chemically reduces the As oxides from the as-received GaAs, while Ga oxide species remain. HCl and S-treated GaAs similarly show no As oxides, and a much smaller degree of Ga oxides than the as-received case. The Ga-S bonding may be responsible for lowering the tendency towards Ga oxidation for the S-treated case. On p-type, Zn-doped GaAs, 3.0 nm lanthanum silicate films produce MOS device EOT values of 2.38 nm, 1.51 nm, and 1.37 nm, on as-received, HCl-treated, and S-treated substrates, respectively. The high EOT for the as-received GaAs corresponds to the thicker Ga oxide and elemental As at the interface. The decreases in both Ga oxide and elemental As at the interface of the S-treated stack appears to be related to it having the lowest EOT devices.


2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.


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