Compact Surface Potential Model for FD SOI MOSFET Considering Substrate Depletion Region

2008 ◽  
Vol 55 (3) ◽  
pp. 789-795 ◽  
Author(s):  
Pradeep Agarwal ◽  
Govind Saraswat ◽  
M. Jagadesh Kumar
Keyword(s):  
Surface Potential ◽  
Potential Model ◽  
Depletion Region ◽  
Compact Surface ◽  
Soi Mosfet

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

A surface potential-model based parameter extraction of Si–Ge-pocket n-TFET

2021 ◽  
Author(s):  
Sagarika Choudhury ◽  
Krishna Lal Baishnab ◽  
Koushik Guha ◽  
Jacopo Iannacci
Keyword(s):  
Surface Potential ◽  
Potential Model ◽  
Parameter Extraction ◽  
Model Based
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